IP Library › Granted Patent US 12,482,668
Granted Patent B2
US 12,482,668 · App. 18/150,398 · Granted Nov 25, 2025

Integrated circuit with getter layer for hydrogen entrapment

Inventors: Marc L. Tarabbia (Austin, TX); Scott P. Warrick (Austin, TX); Winston S. Blackley (Austin, TX)
Assignee: CIRRUS LOGIC, INC.
H01L21/3221H01L21/02172H01L21/02337H01L21/31144H01L21/56H01L21/707H01L23/3107H01L23/5226H10D1/474H10D86/85
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Quick Facts
Patent No.
US 12,482,668
App. No.
18/150,398
Granted
Nov 25, 2025
Kind
B2
Abstract

An integrated circuit (IC) substrate manufacturing process provides time-dependent device characteristic variation due to hydrogen absorption by including one or more gettering layers near the devices that would otherwise absorb hydrogen and exhibit the variation as the hydrogen migrates in the devices. The method includes forming or mounting the devices on a top surface of the semiconductor wafer in die areas of the substrate, forming semiconductor structures in the semiconductor die areas, forming a getter layer above or adjacent to the devices in the die areas, and processing the wafer with one or more processes exposing the wafer to vapor having a hydrogen content, whereby an amount of hydrogen absorbed by the devices is reduced by presence of the getter layer. The method produces wafers including semiconductor dies with reduced hydrogen absorption by the devices and packaged ICs including the dies.

Claims (34)

1 . A method of reducing time-dependent variation of characteristics of thin-film resistors mounted or formed on a substrate of a semiconductor wafer during fabrication due to hydrogen absorption, the method comprising:

forming a first getter layer on the semiconductor wafer in mounting or formation areas of the thin-film resistors in die areas of the substrate;

forming a first insulating layer atop the first getter layer;

subsequent to the forming of the first getter layer, forming or mounting the thin-film resistors on the first insulating layer above the first getter layer above a top surface of the semiconductor wafer in the die areas of the substrate, wherein the thin-film resistors are of a material that absorbs hydrogen and exhibits an electrical characteristic change dependent on an amount of absorbed hydrogen;

forming semiconductor structures in the die areas;

forming a second insulating layer on a top surface of the thin-film resistors in the die areas;

forming a second getter layer on the second insulating layer from an insulating material; and

processing the semiconductor wafer with one or more processes exposing the semiconductor wafer to vapor having a hydrogen content, whereby an amount of hydrogen absorbed by the thin-film resistors is reduced by presence of the getter layer.

2 . The method of claim 1 , wherein the forming or mounting the thin-film resistors forms or mounts tantalum nitride thin-film or silicon-chromium resistors on the semiconductor wafer.

3 . The method of claim 1 , wherein the material of the second getter layer is a metal oxide.

4 . The method of claim 1 , wherein the second getter layer is formed only above a top surface of the insulating layer in areas of the thin-film resistors.

5 . The method of claim 1 , further comprising:

masking the first getter layer around the thin-film resistors to provide for passage of hydrogen beneath the first getter layer; and

removing unmasked portions of the first getter layer.

6 . A semiconductor wafer, comprising:

a base wafer;

a plurality of thin-film resistors mounted or formed in die areas on a top side of the base wafer, wherein the thin-film resistors are of a material that absorbs hydrogen and exhibits an electrical characteristic change dependent on an amount of absorbed hydrogen;

a first getter layer formed on the base wafer in mounting or formation areas of the thin-film resistors in the die areas;

first insulating layer formed on a top surface of the thin film resistors in the die areas;

semiconductor structures formed on the top side of the base wafer in die areas of the base wafer;

a second insulating layer atop the first getter layer, wherein the thin-film resistors are formed or mounted on the second insulating layer; and

a second getter layer formed from an insulating material disposed above or adjacent to the first insulating layer.

7 . The semiconductor wafer of claim 6 , wherein the plurality of thin-film resistors are tantalum nitride or silicon chromium thin-film resistors.

8 . The semiconductor wafer of claim 6 , wherein the insulating material is a metal oxide.

9 . The semiconductor wafer of claim 6 , wherein the second getter layer is only disposed above a top surface of the first insulating layer in areas of the thin-film resistors.

10 . The semiconductor wafer of claim 6 , wherein the second getter layer is restricted to areas around the thin-film resistors to provide for passage of hydrogen through gaps in the first getter layer during fabrication.

11 . An integrated circuit, comprising:

a semiconductor die having a thin-film resistor mounted or formed on a substrate thereof, wherein the thin-film resistor is of a material that absorbs hydrogen and exhibits an electrical characteristic change dependent on an amount of absorbed hydrogen, wherein the semiconductor die includes one or more semiconductor structures formed on the top side of the substrate of the die, a first getter layer on the die in a mounting or formation area of the thin-film resistor, a first insulating layer formed atop the first getter layer, wherein the thin-film resistor is formed or mounted on the first insulating layer, a second insulating layer formed atop the thin-film resistor, and a second getter layer formed from an insulating material disposed on the second insulating layer;

an encapsulation formed around the die; and

a plurality of terminals provided on one or more external surfaces of the encapsulation and connected to electrical terminals of the die.

12 . The integrated circuit of claim 11 , wherein the thin-film resistor is a tantalum nitride or silicon-chromium thin-film resistor.

13 . The integrated circuit of claim 11 , wherein the insulating material is a metal oxide.

14 . The integrated circuit of claim 11 , wherein the getter layer is only disposed above the insulating layer in an area of the thin-film resistor.

15 . The integrated circuit of claim 11 , wherein the second getter layer is restricted to areas around the thin-film resistor to provide for passage of hydrogen during fabrication through gaps in the first getter layer during fabrication.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2025
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 072696/0110 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2023
From: TARABBIA, MARC L.; WARRICK, SCOTT P.; BLACKLEY, WINSTON S.
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 062343/0760 →
Continuity (2)
Provisional Application 63297969 · Jan 10, 2022
Related Publication 20230223274A1 · Jul 13, 2023
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