Timer circuit
A timer circuit including a ramp voltage generator configured to generate a ramp voltage, a comparator coupled on its input side to the ramp voltage generator to receive the ramp voltage and configured to compare the ramp voltage with a switching threshold, and a voltage pulse generating circuit configured to generate a reset signal as a response to a received output signal of the comparator, wherein the reset signal has a shorter time duration than an intrinsic reset time duration of the comparator.
1. A timer circuit, comprising:
a ramp voltage generator configured to generate a ramp voltage;
a comparator coupled on its input side to the ramp voltage generator to receive the ramp voltage and configured to compare the ramp voltage with a switching threshold; and
a voltage pulse generating circuit configured to generate a reset signal as a response to a received output signal of the comparator, wherein the reset signal has a shorter time duration than an intrinsic reset time duration of the comparator,
wherein the comparator is further configured to receive the reset signal and to reset the comparator as a response to receiving the reset signal.
2. The timer circuit as claimed in claim 1 ,
wherein the ramp voltage generator is furthermore configured to receive the reset signal.
3. The timer circuit as claimed in claim 2 ,
wherein the ramp voltage generator is furthermore configured to reset the ramp voltage generator as a response to receiving the reset signal.
4. The timer circuit as claimed in claim 3 ,
wherein the ramp voltage generator comprises a first capacitor and the resetting comprises discharging the first capacitor.
5. A timer circuit, comprising:
a ramp voltage generator configured to generate a ramp voltage;
a comparator coupled on its input side to the ramp voltage generator to receive the ramp voltage and configured to compare the ramp voltage with a switching threshold; and
a voltage pulse generating circuit configured to generate a reset signal as a response to a received output signal of the comparator, wherein the reset signal has a shorter time duration than an intrinsic reset time duration of the comparator,
wherein the ramp voltage generator is further configured to receive the reset signal, and reset the ramp voltage generator as a response to receiving the reset signal,
wherein the ramp voltage generator comprises a first capacitor and the resetting comprises discharging the first capacitor, and
wherein the time duration of the reset signal is at least as long as a discharge duration of the first capacitor.
6. The timer circuit as claimed in claim 4 ,
wherein the ramp voltage generator comprises a transistor; and
wherein the reset signal is configured to switch the transistor to discharge the first capacitor.
7. A timer circuit, comprising:
a ramp voltage generator configured to generate a ramp voltage;
a comparator coupled on its input side to the ramp voltage generator to receive the ramp voltage and configured to compare the ramp voltage with a switching threshold; and
a voltage pulse generating circuit configured to generate a reset signal as a response to a received output signal of the comparator, wherein the reset signal has a shorter time duration than an intrinsic reset time duration of the comparator,
wherein the voltage pulse generating circuit comprises a logic gate having a first input, a second input, and an output, and the voltage pulse generating circuit is configured to feed a signal corresponding to the output signal of the comparator to the first input, which defines a start of the reset signal, and to feed a signal corresponding to the output signal of the comparator to the second input with a time delay, which defines an end of the reset signal, wherein the logic gate is an AND gate, and
wherein the signal corresponding to the output signal of the comparator and provided at the second input with a time delay is an inverted signal with respect to the output signal of the comparator.
8. The timer circuit as claimed in claim 4 ,
wherein the voltage pulse generating circuit comprises a second capacitor.
9. The timer circuit as claimed in claim 8 ,
wherein the second capacitor is configured to set the time duration of the voltage pulse such that it is at least as long as a discharge duration of the first capacitor.
10. The timer circuit as claimed in claim 8 ,
wherein a voltage difference between a state of charge and a state of discharge is greater for the second capacitor than for the first capacitor.
11. The timer circuit as claimed in claim 1 ,
wherein the switching threshold is formed by a reference voltage, a Schmitt trigger, or an inverter.