Power reduction for systems having multiple ranks of memory
Provided are electronic devices and methods for power reduction in systems with multiple memory ranks. The electronic device includes a memory system including first and second memory ranks and a memory controller connected to the memory system and configured to control power of the memory system. The memory controller being configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank.
1. An electronic device comprising:
a memory system including first and second memory ranks; and
a memory controller connected to the memory system and configured to control power of the memory system,
the memory controller further configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank; and
wherein the IPD minimum gain duration includes a rank-to-rank switching time, a per-bank refresh cycle time and a delay time from issuance of an active command to application of a write/read command.
2. The electronic device of claim 1 , wherein the other bank access is configured to be performed between different bank groups of the second memory rank.
3. The electronic device of claim 1 , wherein
the memory controller is configured to cause the first memory rank to enter the IPD state by performing a downcounting operation using a count value, and
the count value is set as a waiting time for preparing for a possibility of an access request for the first memory rank or the second memory rank before entering the IPD state.
4. The electronic device of claim 1 , wherein the memory controller is configured to cause the first memory rank to enter the IPD state during memory access in which a page hit and miss processing time of the second memory rank is equal to or greater than the IPD minimum gain duration.
5. The electronic device of claim 1 , wherein the memory controller is configured to postpone a refresh operation of the first memory rank during the IPD minimum gain duration, and cause the first memory rank to enter the IPD state.
6. The electronic device of claim 5 , wherein the memory controller is configured to set a refresh postpone period of the first memory rank to be greater than the IPD minimum gain duration.
7. The electronic device of claim 1 , wherein the memory controller is configured to pull in a refresh operation of the first memory rank before the first memory rank enters the IPD state.
8. The electronic device of claim 1 , wherein the memory controller is configured to pull in a refresh operation of the first and second memory ranks during a memory training operation period for the first and second memory ranks.
9. The electronic device of claim 1 , wherein the memory controller is configured to pull in a refresh operation of the first and second memory ranks during a delay locked loop update of a memory physical layer connected to the first and second memory ranks.
10. The electronic device of claim 1 , wherein the memory controller is configured to pull in a refresh operation of the first and second memory ranks based on a read operation and a write operation being switched to each other from the first memory rank to the second memory rank.
11. The electronic device of claim 1 , wherein the memory controller is configured to pull in a refresh operation of a corresponding rank based on a read operation and a write operation being switched to each other in each of the first and second memory ranks.
12. The electronic device of claim 1 , wherein the memory controller is configured to pull in a refresh operation of a corresponding rank for a delay time due to a page miss or collision in each of the first and second memory ranks.
13. The electronic device of claim 1 , wherein the memory controller is configured to reorder a refresh order for banks of the first and second memory ranks waiting in a request queue before the first memory rank enters the IPD state.
14. An electronic device comprising:
a memory system including first and second memory ranks;
a memory controller connected to the memory system and configured to control power of the memory system,
the memory controller further configured to cause the first memory rank to enter an active power down (APD) state based on there being an open page for the first memory rank during memory access in which a data toggle time without a data bubble is shorter than an idle power-down (IPD) minimum gain duration in another bank access for the second memory rank; and
wherein the IPD minimum gain duration includes a rank-to-rank switching time, a per-bank refresh cycle time and a delay time from issuance of an active command to application of a write/read command.
15. The electronic device of claim 14 , wherein the other bank access is configured to be performed between different bank groups of the second memory rank.
16. The electronic device of claim 14 , wherein
the memory controller is configured to cause the first memory rank to enter the APD state by performing a downcounting operation using a count value, and
the count value is set as a waiting time for preparing for a possibility of an access request for the first memory rank or the second memory rank before entering the APD state.
17. The electronic device of claim 14 , wherein the memory controller is configured to cause the first memory rank to enter the APD state during memory access in which the data toggle time without a bubble is greater than an APD minimum gain duration for the second memory rank.
18. The electronic device of claim 14 , wherein the memory controller is configured to cause the first memory rank to enter the APD state during memory access in which a page hit processing time according to a page hit state of the first memory rank is shorter than an tRCD+RL time that is a sum of a last-to-cas delay time and a read latency time, based on there being no open page for the first memory rank during the data toggle time without the data bubble for the second memory rank.
19. The electronic device of claim 18 , wherein the memory controller is configured to cause the first memory rank to enter the APD state during memory access in which the page hit processing time based on any one page of the first memory rank being closed is shorter than the tRCD+RL time, in response to memory accessing in which the page hit processing time of the first memory rank is greater than the tRCD+RL time.
20. The electronic device of claim 19 , wherein the memory controller is configured to close a page having a relatively low priority during scheduling the first memory rank.