IP Library Granted Patent US 12,300,558
Granted Patent B2
US 12,300,558 · App. 18/160,450 · Granted May 13, 2025

Substrates and related methods

Inventors: Atapol Prajuckamol (Thanyaburi, TH); Chee Hiong Chew (Seremban, MY); Yushuang Yao (Shenzhen, CN); Vemmond Jeng Hung Ng (Senawang, MY)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/13B32B3/02B32B9/005B32B9/041B32B15/20H01L21/4871H01L23/3735B32B2250/03B32B2250/40B32B2307/206B32B2457/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,300,558
App. No.
18/160,450
Granted
May 13, 2025
Kind
B2
Abstract

Implementations of a substrate may include an electrically insulative layer having a first largest planar side and a second largest planar side opposing the first largest planar side; a first electrically conductive layer coupled to the first largest planar side and including a first scalloped edge having a first pattern; and a second electrically conductive layer coupled to the second largest planar side and including a second scalloped edge having a second pattern. The first pattern and the second pattern may alternate along at least one edge of the first largest planar side and at least one edge of the second largest planar side, respectively.

Claims (28)

1. A substrate comprising:

an electrically insulative layer having a first largest planar side and a second largest planar side opposing the first largest planar side;

a first electrically conductive layer coupled to the first largest planar side and comprising a first scalloped edge having a first pattern; and

a second electrically conductive layer coupled to the second largest planar side and comprising a second scalloped edge having a second pattern;

wherein the first pattern and the second pattern alternate along at least one edge of the first largest planar side and at least one edge of the second largest planar side, respectively.

2. The substrate of claim 1 , wherein the first pattern is periodic.

3. The substrate of claim 1 , wherein the second pattern is periodic.

4. The substrate of claim 1 , wherein the first pattern comprises repeating angular projections.

5. The substrate of claim 1 , wherein the second pattern comprises repeating angular projections.

6. The substrate of claim 2 , wherein the second pattern is periodic.

7. The substrate of claim 4 , wherein the second pattern comprises repeating angular projections.

8. A substrate comprising:

an electrically insulative layer having a first largest planar side and a second largest planar side opposing the first largest planar side;

a first electrically conductive layer coupled to the first largest planar side and comprising a first scalloped edge having a first pattern; and

a second electrically conductive layer coupled to the second largest planar side and comprising a second scalloped edge having a second pattern, the second pattern alternating with the first pattern.

9. The substrate of claim 8 , wherein the first pattern is periodic.

10. The substrate of claim 8 , wherein the second pattern is periodic.

11. The substrate of claim 8 , wherein the first pattern comprises repeating angular projections.

12. The substrate of claim 8 , wherein the second pattern comprises repeating angular projections.

13. The substrate of claim 9 , wherein the second pattern is periodic.

14. The substrate of claim 11 , wherein the second pattern comprises repeating angular projections.

15. A substrate comprising:

an electrically insulative layer having a first largest planar side and a second largest planar side opposing the first largest planar side;

a first electrically conductive layer coupled to the first largest planar side and comprising a first scalloped edge having a first sinusoidal pattern; and

a second electrically conductive layer coupled to the second largest planar side and comprising a second scalloped edge having a second sinusoidal pattern;

wherein the first sinusoidal pattern and the second sinusoidal pattern alternate along at least one edge of the first largest planar side and at least one edge of the second largest planar side, respectively.

16. The substrate of claim 15 , wherein the first sinusoidal pattern is 180 degrees out of phase with the second sinusoidal pattern.

17. The substrate of claim 15 , wherein the first scalloped edge overlaps the second scalloped edge only at recessed locations of the first scalloped edge and recessed locations of the second scalloped edge.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 064502, FRAME 0293 Recorded Nov 14, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 065566/0488 →
SECURITY INTEREST Recorded May 9, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 065402/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2023
From: PRAJUCKAMOL, ATAPOL; CHEW, CHEE HIONG; YAO, YUSHUANG; NG, VEMMOND JENG HUNG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 062508/0878 →