Serial receiver circuit with follower skew adaptation

1. An apparatus, comprising:

a front-end circuit configured to generate an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;

an analog receiver circuit configured to sample, using a plurality of first clock signals, the equalized signal to generate a plurality of first samples;

a clock generator circuit configured to:

generate the plurality of first clock signals using first phase information based on a phase difference between the plurality of first clock signals and the plurality of first samples; and

generate a plurality of second clock signals using the first phase information; and

an analog-to-digital converter (ADC)-based receiver circuit that includes an analog-to-digital converter circuit wherein the ADC-based receiver circuit is configured to sample the equalized signal using the plurality of second clock signals to generate a plurality of recovered data symbols.

2. The apparatus of claim 1 , wherein the clock generator circuit is further configured to generate the plurality of second clock signals using second phase information based on a second phase difference between the plurality of second clock signals and the plurality of recovered data symbols.

3. The apparatus of claim 2 , wherein the analog receiver circuit includes a bang-bang phase detector circuit configured to:

perform a phase comparison operation between the plurality of first clock signals and the plurality of first samples; and

generate the first phase information and the second phase information using a result of the phase comparison operation.

4. The apparatus of claim 2 , wherein the ADC-based receiver circuit includes a Mueller-Muller phase detector circuit configured to:

perform a phase comparison operation between the plurality of second clock signals and the plurality of recovered data symbols; and

generate the first phase information using a result of the phase comparison operation.

5. The apparatus of claim 1 , wherein the clock generator circuit is further configured, in response to an activation of a foreground calibration operation, sweep, through a series of phase values, respective phases of the plurality of second clock signals relative to the plurality of first clock signals.

6. The apparatus of claim 5 , wherein the ADC-based receiver circuit includes a phase adjustment circuit configured, in response to an activation of a background calibration operation, to:

adapt relative phases of the plurality of second clock signals; and

sample the equalized signal at each of the series of phase values to generate a plurality of calibration samples; and

wherein the clock generator circuit is further configured, in response to the activation of the background calibration operation, to adjust the respective phases of the plurality of second clock signals using the plurality of calibration samples relative to the plurality of first clock signals.

7. A method, comprising:

generating, by a front-end circuit, an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;

sampling, by an analog receiver circuit using a plurality of first clock signals, the equalized signal to generate a plurality of first samples;

generating, by a clock generator circuit, the plurality of first clock signals using first phase information based on a phase difference between the plurality of first clock signals and the plurality of first samples;

generating, by the clock generator circuit, a plurality of second clock signals using the first phase information; and

sampling, by an analog-to-digital converter (ADC)-based receiver circuit, the equalized signal using the plurality of second clock signals to generate a plurality of recovered data symbols, wherein the ADC-based receiver circuit includes an analog-to-digital converter circuit.

8. The method of claim 7 , further comprising generating, by the clock generator circuit, the plurality of second clock signals using second phase information based on a second phase difference between the plurality of second clock signals and the plurality of recovered data symbols.

9. The method of claim 8 , further comprising:

performing, by a bang-bang phase detector circuit included in the analog receiver circuit, a phase comparison operation between the plurality of first clock signals and the plurality of first samples; and

generating, by the analog receiver circuit, the first phase information using a result of the phase comparison operation.

10. The method of claim 8 , further comprising:

performing, by a Mueller-Muller phase detector circuit included in the ADC-based receiver circuit, a phase comparison operation between the plurality of second clock signals and the plurality of recovered data symbols; and

generating, by the ADC-based receiver circuit, the first phase information using a result of the phase comparison operation.

11. The method of claim 7 , further comprising, in response to an activation of a foreground calibration operation:

sampling, by the analog receiver circuit, an equalized version of a test signal using the plurality of first clock signals to generate a plurality of test samples; and

adjusting, by the clock generator circuit, respective phases of the plurality of first and second clock signals using the plurality of test samples.

12. The method of claim 11 , further comprising:

in response to an activation of a background calibration operation:

adapting relative phases of the plurality of second clock signals;

sampling the equalized signal at each of a series of phase values to generate a plurality of calibration samples; and

adjusting the respective phases of the second clock signals relative to the plurality of first clock signals using the plurality of calibration samples.

13. The method of claim 7 , wherein generating the plurality of first clock signals includes tuning an oscillator circuit included in the clock generator circuit using the first phase information.

14. An apparatus, comprising:

a first device that includes a first functional circuit block, wherein the first device is configured to:

receive, from the first functional circuit block, a serial data stream that includes a plurality of data symbols;

generate a plurality of signals that encode the serial data stream; and

transmit the plurality of signals via a communication channel; and

a second device coupled to the first device via the communication channel, wherein the second device includes a plurality of receiver circuits, and wherein the second device is configured to generate an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols; and

wherein a first receiver circuit of the plurality of receiver circuits, that includes an analog receiver circuit, is configured to sample using a plurality of first clock signals, the equalized signal to generate a plurality of first samples;

wherein a second receiver circuit of the plurality of receiver circuits, that includes an analog-to-digital converter circuit, is configured to sample the equalized signal using a plurality of second clock signals to generate a plurality of recovered data symbols; and

wherein the second device is further configured to:

generate the plurality of first clock signals using first phase information based on a phase difference between the plurality of first clock signals and the plurality of first samples; and

generate the plurality of second clock signals using the first phase information.

15. The apparatus of claim 14 , wherein the second device is further configured to generate the plurality of second clock signals using second phase information based on a second phase difference between the plurality of second clock signals and the plurality of recovered data symbols.

16. The apparatus of claim 15 , wherein the first receiver circuit includes a bang-bang phase detector circuit configured to perform a phase comparison operation between the plurality of first clock signals and the plurality of first samples, and wherein the first receiver circuit is further configured to generate the first phase information using a result of the phase comparison operation.

17. The apparatus of claim 15 , wherein the second receiver circuit includes a Mueller-Muller phase detector circuit configured to perform a phase comparison operation between the plurality of second clock signals and the plurality of recovered data symbols, and wherein the second receiver circuit is configured to generate the first phase information using a result of the phase comparison operation.

18. The apparatus of claim 14 , wherein the second device is configured, in response to an activation of a foreground calibration operation to:

sweep, through a series of phase values, respective phases of the plurality of second clock signal relative to the plurality of first clock signals;

sample an equalized version of a test signal using the plurality of second clock signals to generate a plurality of test samples; and

select a particular phase offset for the plurality of second clock signals using the plurality of test samples.

19. The apparatus of claim 14 , wherein the second device is configured, in response to an activation of a background calibration operation, to adapt respective phases of the plurality of second clock signals relative to the plurality of first clock signals.

20. The apparatus of claim 14 , wherein the second device includes an oscillator circuit, and wherein to generate the plurality of first clock signals, the second device is further configured to tune the oscillator circuit using the first phase information.