Dummy data-based read reference voltage search of NAND memory
A method can include performing a single-read operation at a read reference voltage to detect bits from memory cells. Dummy data is previously programmed into the memory cells. Original bits of the memory cells can be determined based on a default read reference voltage and known values of the dummy data. The detected bits and the original bits are compared to determine an upper-state failed bit count (FBC) corresponding to the memory cells having threshold voltages shifted from above the read reference voltage to below the read reference voltage and a lower-state FBC corresponding to the memory cells having threshold voltages shifted from below the read reference voltage to above the read reference voltage. When a difference between the upper-state FBC and the lower-state FBC being smaller than a threshold, the read reference voltage can be determined to be a best read reference voltage.
1. A method, comprising:
performing a single-read operation at a read reference voltage of a first level to detect bits from a set of memory cells in a memory device, dummy data being previously programmed into the set of memory cells;
determining original bits of the set of memory cells based on a default read reference voltage and known values of the dummy data, the original bits corresponding to initial threshold voltages of the set of memory cells when the dummy data is initially programmed into the set of memory cells;
comparing the detected bits and the original bits to determine an upper-state failed bit count (FBC) and a lower-state FBC, the upper-state FBC being a first number of flipping bits that correspond to the memory cells having threshold voltages shifted from above the read reference voltage to below the read reference voltage, the lower-state FBC being a second number of flipping bits that correspond to the memory cells having threshold voltages shifted from below the read reference voltage to above the read reference voltage; and
in response to a difference between the upper-state FBC and the lower-state FBC being smaller than a threshold, determining the read reference voltage of the first level to be a best read reference voltage.
2. The method of claim 1 , further comprising:
in response to the difference between the upper-state FBC and the lower-state FBC being larger than the threshold, and the lower-state FBC being smaller than the upper-state FBC, performing the steps of the performing, the determining, and the comparing using the read reference voltage of a second level smaller than the first level.
3. The method of claim 2 , wherein the read reference voltage is increased or decreased based on a fixed step voltage.
4. The method of claim 1 , further comprising:
in response to the difference between the upper-state FBC and the lower-state FBC being larger than the threshold, and the lower-state FBC being larger than the upper-state FBC, performing the steps of the performing, the determining, and the comparing using the read reference voltage of a third level larger than the first level.
5. The method of claim 4 , wherein the read reference voltage is increased or decreased based on a fixed step voltage.
6. The method of claim 4 , wherein in response to the difference between the upper-state FBC and the lower-state FBC being outside of a predefined range, the read reference voltage is increased or decreased based on a first step voltage, and
in response to the difference between the upper-state FBC and the lower-state FBC being inside of the predefined range, the read reference voltage is increased or decreased based on a second step voltage smaller than the first step voltage.
7. The method of claim 1 , wherein the method is performed as a background operation.
8. The method of claim 1 , wherein the method is triggered in response to a host read request, and the best read reference voltage is used as an initial read reference voltage for reading data from the memory device.
9. The method of claim 1 , wherein the method is triggered after an error correction code (ECC) decoding fails.
10. The method of claim 9 , further comprising:
using the best read reference voltage as a read-retry voltage for reading data from the memory device, or
using the best read reference voltage as a base voltage for a soft decode process for reading data from the memory device.
11. The method of claim 1 , further comprising:
in response to a failure of an ECC decoding for reading a current page, determining one of:
the current page including the dummy data,
a neighboring page of the current page including the dummy data,
a word line group that includes the current page including the dummy data, and
the current page belonging to a super page that includes the dummy data in a plane or a die different from a plane or a die of the current page; and
using the best read voltage as a reference voltage for reading the current page.
12. The method of claim 1 , wherein the dummy data is one of:
data of codewords that belong to multiple pages that are stored in a horizontal memory cell string including memory cells associated with a word line, and
data of multiple pages that are stored in a horizontal memory cell string including memory cells associated with a word line.
13. The method of claim 1 , further comprising:
determining a block in the memory device to be a weak block that is more vulnerable to flipping bit errors than another block in the memory device; and
writing the dummy data to the block.
14. The method of claim 1 , further comprising:
using the best read voltage as a reference read voltage for one of:
reading a code word stored in a same page as the dummy data,
reading a page neighboring a page including the dummy data,
reading a page belonging to a word line group that includes the dummy data,
reading a page that belongs to a same super page as the dummy data and is stored in a plane or die different from a plan or die where the dummy data is stored.
15. The method of claim 1 , wherein the method is performed by a solid-state drive (SSD) controller.
16. The method of claim 1 , wherein the method is performed by circuitry in the memory device.
17. A memory controller, comprising circuitry configured to:
perform a single-read operation at a read reference voltage of a first level to detect bits from a set of memory cells in a memory device, dummy data being previously programmed into the set of memory cells;
determine original bits of the set of memory cells based on a default read reference voltage and known values of the dummy data, the original bits corresponding to initial threshold voltages of the set of memory cells when the dummy data is initially programmed into the set of memory cells;
compare the detected bits and the original bits to determine an upper-state failed bit count (FBC) and a lower-state FBC, the upper-state FBC being a first number of flipping bits that correspond to the memory cells having threshold voltages shifted from above the read reference voltage to below the read reference voltage, the lower-state FBC being a second number of flipping bits that correspond to the memory cells having threshold voltages shifted from below the read reference voltage to above the read reference voltage; and
in response to a difference between the upper-state FBC and the lower-state FBC being smaller than a threshold, determine the read reference voltage of the first level to be a best read reference voltage.
18. The memory controller of claim 17 , wherein the circuitry is further configured to:
in response to the difference between the upper-state FBC and the lower-state FBC being larger than the threshold, and the lower-state FBC being smaller than the upper-state FBC, perform the steps of the performing, the determining, and the comparing using the read reference voltage of a second level smaller than the first level.
19. The memory controller of claim 17 , wherein the circuitry is further configured to:
in response to the difference between the upper-state FBC and the lower-state FBC being larger than the threshold, and the lower-state FBC being larger than the upper-state FBC, perform the steps of the performing, the determining, and the comparing using the read reference voltage of a third level larger than the first level.
20. A memory system, comprising:
a memory device; and
a memory controller configured to:
perform a single-read operation at a read reference voltage of a first level to detect bits from a set of memory cells in the memory device, dummy data being previously programmed into the set of memory cells;
determine original bits of the set of memory cells based on a default read reference voltage and known values of the dummy data, the original bits corresponding to initial threshold voltages of the set of memory cells when the dummy data is initially programmed into the set of memory cells;
compare the detected bits and the original bits to determine an upper-state failed bit count (FBC) and a lower-state FBC, the upper-state FBC being a first number of flipping bits that correspond to the memory cells having threshold voltages shifted from above the read reference voltage to below the read reference voltage, the lower-state FBC being a second number of flipping bits that correspond to the memory cells having threshold voltages shifted from below the read reference voltage to above the read reference voltage; and
in response to a difference between the upper-state FBC and the lower-state FBC being smaller than a threshold, determine the read reference voltage of the first level to be a best read reference voltage.