IP Library Granted Patent US 12,287,747
Granted Patent B2
US 12,287,747 · App. 18/162,972 · Granted Apr 29, 2025

Fast device reinitialization on DSI3 bus

Inventor: Marek Hustava (Bratislava, SK)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G06F13/404
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Quick Facts
Patent No.
US 12,287,747
App. No.
18/162,972
Granted
Apr 29, 2025
Kind
B2
Abstract

Accordingly, there is disclosed herein host device and bus communication method that enables fast sensor device reinitialization that minimizes outage time associated with an unexpected device reset. One illustrative bus communication method includes: providing each of one or more slave devices with a dynamically-determined bus address; querying each of the dynamically-determined bus addresses to obtain a unique device identifier associated with that dynamically-determined bus address; receiving a sequence of data frames each having time-division multiplexed data from the one or more slave devices; and between data frames in the sequence, checking to determine whether any of the one or more slave devices has been reset.

Claims (33)

1. A bus communication method that comprises:

providing each of one or more slave devices with a dynamically-determined bus address;

querying each of the dynamically-determined bus addresses to obtain, for each of the dynamically-determined bus addresses, an associated unique device identifier;

receiving a sequence of data frames each having time-division multiplexed data from the one or more slave devices; and

between data frames in the sequence, checking to determine whether any of the one or more slave devices has been reset by attempting to retrieve a unique device identifier from a default bus address.

2. The bus communication method of claim 1 , further comprising:

responsive to said attempting, receiving a unique device identifier of a reset slave device.

3. The bus communication method of claim 2 , further comprising:

determining a dynamically-determined bus address previously associated with the unique device identifier of the reset slave device; and

configuring the reset slave device with its previously associated dynamically-determined bus address.

4. The bus communication method of claim 3 , wherein said configuring includes writing register data to the default bus address.

5. The bus communication method of claim 4 , wherein said register data includes additional configuration data for the reset slave device.

6. The bus communication method of claim 4 , further comprising writing additional configuration data to the previously associated dynamically-determined bus address after said configuring and before receiving a subsequent data frame in said sequence.

7. The bus communication method of claim 1 , wherein a next data frame in the sequence is initiated when a timeout results from said checking.

8. The communications method of claim 1 , wherein the unique device identifier is a device level traceability (DLT) code.

9. A bus master device that comprises:

a driver configured to drive a downlink signal on a bus signal line;

a receive buffer configured to sense an uplink signal on the bus signal line;

a controller coupled to the driver and the receiver buffer, the controller being configured to implement a communication method via the bus signal line, the method including:

providing each of one or more slave devices with a dynamically-determined bus address;

querying each of the dynamically-determined bus addresses to obtain, for each of the dynamically-determined bus addresses, an associated unique device identifier;

receiving a sequence of data frames each having time-division multiplexed data from the one or more slave devices; and

between data frames in the sequence, checking to determine whether any of the one or more slave devices has been reset by attempting to retrieve a unique device identifier from a default bus address.

10. The bus master device of claim 9 , the communication method further comprising:

responsive to said attempting, receiving a unique device identifier of a reset slave device.

11. The bus master device of claim 10 , the communication method further comprising:

determining a dynamically-determined bus address previously associated with the unique device identifier of the reset slave device; and

configuring the reset slave device with its previously associated dynamically-determined bus address.

12. The bus master device of claim 11 , wherein said configuring includes writing register data to the default bus address.

13. The bus master device of claim 12 , wherein said register data includes additional configuration data for the reset slave device.

14. The bus master device of claim 12 , the communication method further comprising writing additional configuration data to the previously associated dynamically-determined bus address after said configuring and before receiving a subsequent data frame in said sequence.

15. The bus master device of claim 9 , wherein a next data frame in the sequence is initiated when a timeout results from said checking.

16. The bus master device of claim 9 , wherein the unique device identifier is a device level traceability (DLT) code.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 064502, FRAME 0293 Recorded Nov 14, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 065566/0488 →
SECURITY INTEREST Recorded May 9, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 065402/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2023
From: HUSTAVA, MAREK
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 062562/0095 →