Granted Patent B1

US 12,547,916 · App. 18/164,436 · Granted Feb 10, 2026

Inventors: Chad Tyler Rigetti (Walnut Creek, CA); Dane Christoffer Thompson (Granite Bay, CA); Alexei N. Marchenkov (Walnut Creek, CA); Mehrnoosh Vahidpour (El Cerrito, CA); Eyob A. Sete (Walnut Creek, CA); Matthew J. Reagor (San Rafael, CA)

Assignee: Rigetti & Co, LLC

G06N10/00H01L21/76877H01L21/76891H01L21/76898H10N60/12H10N60/815H10N69/00B82Y10/00H01L2225/06541H01L2225/1041Y10S977/933

Abstract

Claims (37)

1 . A quantum processing unit comprising:

a quantum processor cell comprising a plurality of stacked circuit wafers, the plurality of stacked circuit wafers comprising:

a first circuit wafer comprising first quantum circuitry disposed on a surface of the first circuit wafer, the first quantum circuitry comprising a plurality of qubit devices; and

a second circuit wafer comprising second quantum circuitry disposed on a surface of the second circuit wafer, the second quantum circuitry comprising a plurality of filters;

a third circuit wafer comprising a plurality of recesses, a plurality of standoff bumps, and an electrically conducting layer that conforms to the plurality of recesses and the plurality of standoff bumps; and

routing circuitry that couples the first quantum circuitry and the second quantum circuitry.

2 . The quantum processing unit of claim 1 , wherein the plurality of stacked circuit wafers further comprises:

a fourth circuit wafer comprising third quantum circuitry disposed on a surface of the fourth circuit wafer, the third quantum circuitry comprising a plurality of readout devices; and

routing circuitry that couples the third quantum circuitry and at least one of the first or second quantum circuitry.

3 . The quantum processing unit of claim 2 , wherein the plurality of readout devices comprises a plurality of linear resonators.

4 . The quantum processing unit of claim 2 , wherein the plurality of readout devices comprises a plurality of non-linear resonators.

5 . The quantum processing unit of claim 1 , wherein the plurality of stacked circuit wafers further comprises:

a fourth circuit wafer comprising third quantum circuitry disposed on a surface of the fourth circuit wafer, the third quantum circuitry comprising a plurality of quantum amplifiers; and

routing circuitry that couples the third quantum circuitry and at least one of the first or second quantum circuitry.

6 . The quantum processing unit of claim 1 , wherein the plurality of stacked circuit wafers comprises a fourth circuit wafer comprising at least a portion of the routing circuitry.

7 . The quantum processing unit of claim 1 , wherein the first circuit wafer is bonded to the third circuit wafer such that the plurality of recesses form enclosures that house the plurality of qubit devices.

8 . The quantum processing unit of claim 7 , wherein the plurality of standoff bumps comprises one of silicon oxide or silicon nitride.

9 . The quantum processing unit of claim 1 , wherein at least one circuit wafer in the plurality of stacked circuit wafers comprises electrically conducting vias.

10 . The quantum processing unit of claim 1 , wherein the plurality of qubit devices comprises a plurality of transmons.

11 . A method of fabricating a quantum processor cell in a quantum processing unit, the quantum processor cell comprising a plurality of stacked circuit wafers, the method comprising:

forming first quantum circuitry on a surface of a first circuit wafer, the first quantum circuitry comprising a plurality of qubit devices;

forming second quantum circuitry on a surface of a second circuit wafer, the second quantum circuitry comprising a plurality of filters;

forming a plurality of recesses, a plurality of standoff bumps, and an electrically conducting layer that conforms to the plurality of recesses and the plurality of standoff bumps on a third circuit wafer; and

forming a stack of circuit wafers comprising the first circuit wafer, the second circuit wafer, the third circuit wafer, and routing circuitry, wherein the routing circuitry couples the first quantum circuitry on the first circuit wafer with the second quantum circuitry on the second circuit wafer.

12 . The method of claim 11 , comprising:

forming third quantum circuitry on a surface of a fourth circuit wafer, the third quantum circuitry comprising a plurality of readout devices, wherein the stack of circuit wafers comprises the fourth circuit wafer.

13 . The method of claim 12 , wherein the plurality of readout devices comprises a plurality of linear resonators.

14 . The method of claim 12 , wherein the plurality of readout devices comprises a plurality of non-linear resonators.

15 . The method of claim 11 , comprising:

forming third quantum circuitry on a surface of a fourth circuit wafer, the third quantum circuitry comprising a plurality of quantum amplifiers, wherein the stack of circuit wafers comprises the fourth circuit wafer.

16 . The method of claim 11 , wherein the plurality of stacked circuit wafers comprises a fourth circuit wafer, and the method comprises:

forming at least a portion of the routing circuitry on a surface of the fourth circuit wafer.

17 . The method of claim 11 , comprising:

bonding the first circuit wafer to the third circuit wafer such that the plurality of recesses on the third circuit wafer form enclosures that house the plurality of qubit devices on the first circuit wafer.

18 . The method of claim 17 , wherein the plurality of standoff bumps comprises one of silicon oxide or silicon nitride.

19 . The method of claim 11 , wherein at least one circuit wafer in the plurality of stacked circuit wafers comprises electrically conducting vias.

20 . The method of claim 11 , wherein the plurality of qubit devices comprises a plurality of transmons.

Assignments (5)

Continuity (5)

References Cited (400)