IP Library › Granted Patent US 11,973,149
Granted Patent B2
US 11,973,149 · App. 18/164,642 · Granted Apr 30, 2024

Semiconductor device and method of forming the same

Inventors: Yu-Hsing Chang (Taipei, TW); Chern-Yow Hsu (Hsin-Chu County, TW); Shih-Chang Liu (Kaohsiung County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H01L29/94H01L21/0271H01L21/76877H01L23/5223H01L28/40H01L28/87
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Quick Facts
Patent No.
US 11,973,149
App. No.
18/164,642
Granted
Apr 30, 2024
Kind
B2
Abstract

A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed over the second insulating plate; a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the fourth conductive plate and the first conductive plate; and a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate, wherein the second conductive via is electrically coupled to the third conductive plate and the second conductive plate.

Claims (55)

1. A semiconductor device, comprising:

a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate;

a first insulating plate disposed over the first conductive plate and the second conductive plate;

a third conductive plate disposed over the first insulating plate;

a second insulating plate disposed over the third conductive plate;

a fourth conductive plate disposed over the second insulating plate;

a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the fourth conductive plate and the first conductive plate; and

a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate, wherein the second conductive via is electrically coupled to the third conductive plate and the second conductive plate.

2. The semiconductor device of claim 1 , wherein the first insulating plate covers a sidewall of the first conductive plate and a sidewall of the second conductive plate.

3. The semiconductor device of claim 1 , wherein the first insulating plate is in contact with the second insulating plate around the first conductive via.

4. The semiconductor device of claim 1 , further comprising an integrated circuit (IC) device, wherein the first conductive plate and the second conductive plate are arranged over the IC device.

5. The semiconductor device of claim 1 , further comprising:

a fifth conductive plate over the first insulating plate;

a sixth conductive plate over the second insulating plate; and

a third conductive via penetrating the sixth conductive plate, the second insulating plate, the fifth conductive plate, and the first insulating plate, wherein the third conductive via is electrically coupled to the sixth conductive plate and the fifth conductive plate.

6. The semiconductor device of claim 5 , wherein the sixth conductive plate covers a sidewall of the second insulating plate over the fifth conductive plate.

7. The semiconductor device of claim 5 , wherein the second insulating plate laterally surrounds the fifth conductive plate.

8. The semiconductor device of claim 1 , wherein the first insulating plate separates the first conductive plate from the second conductive plate.

9. A semiconductor device, comprising:

a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate;

a first insulating plate disposed over the first conductive plate and the second conductive plate;

a third conductive plate disposed over the first insulating plate and cover the first conductive plate;

a second insulating plate disposed over the third conductive plate;

a fourth conductive plate disposed over the second insulating plate;

a first conductive via electrically coupled to the fourth conductive plate and the first conductive plate; and

a second conductive via electrically coupled to the third conductive plate and the second conductive plate.

10. The semiconductor device of claim 9 , wherein the second insulating plate is exposed through the fourth conductive plate.

11. The semiconductor device of claim 9 further comprising a fifth conductive plate arranged over the second insulating plate on a side of the second conductive via opposite to the fourth conductive plate.

12. The semiconductor device of claim 11 , further comprising an oxide layer laterally surrounding the first conductive via and the second conductive via, and separating the second conductive via from the fifth conductive plate.

13. The semiconductor device of claim 11 , wherein the fourth conductive plate and the fifth conductive plate are formed of a same material.

14. A semiconductor device, comprising:

a first conductive plate and a second conductive plate;

a first insulating plate disposed over the first conductive plate and the second conductive plate;

a third conductive plate disposed over the first insulating plate;

a second insulating plate disposed over the third conductive plate;

a fourth conductive plate disposed over the second insulating plate;

a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate; and

a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate.

15. The semiconductor device of claim 14 , further comprising:

a fifth conductive plate over the first insulating plate;

a sixth conductive plate over the second insulating plate; and

a third conductive via penetrating the sixth conductive plate, the second insulating plate, the fifth conductive plate, and the first insulating plate, wherein the third conductive via is electrically coupled to the sixth conductive plate and the fifth conductive plate.

16. The semiconductor device of claim 15 , wherein the fifth conductive plate and the third conductive plate are formed of a first same material, and the sixth conductive plate and the fourth conductive plate are formed of a second same material.

17. The semiconductor device of claim 14 , further comprising:

a fifth conductive plate;

a sixth conductive plate on the first insulating plate, wherein the second insulating plate is further formed on the sixth conductive plate; and

a third conductive via penetrating the second insulating plate, the sixth conductive plate, the first insulating plate, and the fifth conductive plate, wherein the third conductive via is electrically coupled to the sixth conductive plate and the fifth conductive plate.

18. The semiconductor device of claim 17 , wherein the fifth conductive plate, the first conductive plate, and the second conductive plate are formed of a third same material, and the sixth conductive plate and the third conductive plate are formed of a fourth same material.

19. The semiconductor device of claim 14 , further comprising:

a fifth conductive plate, wherein the first insulating plate is further formed on the fifth conductive plate, and the second insulating plate is further formed on the first insulating plate;

a sixth conductive plate on the second insulating plate; and

a third conductive via penetrating the sixth conductive plate, the first insulating plate, the second insulating plate, and the fifth conductive plate, wherein the third conductive via is electrically coupled to the sixth conductive plate and the fifth conductive plate.

20. The semiconductor device of claim 14 , further comprising:

a first oxide layer below the first conductive plate and the second conductive plate, and

a second oxide layer over the fourth conductive plate and laterally surrounding the first conductive via and the second conductive via.

Continuity (4)
Continuation 17014607 · Sep 8, 2020
Division 16136896 · Sep 20, 2018
Provisional Application 62592288 · Nov 29, 2017
Related Publication 20230187563A1 · Jun 15, 2023
Cited By (1)
US 12,446,238