IP Library › Granted Patent US 12,625,737
Granted Patent B2
US 12,625,737 · App. 18/165,467 · Granted May 12, 2026

Self-recovering method of physical layer of base station and base station apparatus

Inventors: Terng-Yin Hsu (Zhubei City, TW); Yuan-Te Liao (Zhubei City, TW); Shung-Mei Koh (Zhubei City, TW)
Assignee: Aespula Technology INC.
G06F9/505G06F9/4881G06F9/4887H04W24/04H04W28/0908G06F9/5038G06F2209/5022G06F2209/508
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Quick Facts
Patent No.
US 12,625,737
App. No.
18/165,467
Granted
May 12, 2026
Kind
B2
Abstract

A processor of a base station apparatus executes steps of: (a) executing multiple first tasks, one by one, during a time period of one of m time slots in a normal mode in a thread pool; (b) when finishing executing the first tasks, recording first statuses of the first tasks into the task status vector table; (c) when finishing recording the first statuses of the first tasks, determining whether all of second statuses of second tasks of a previous k th time slot of the m time slots recorded in the task status vector table are executed statuses; if yes, returning to the step (a); if not, executing at least one of the second tasks of the previous k th time slot having an unexecuted status within next p consecutive time slots in a load reduction mode, and then returning to step (a); m, k, and p are positive integers. The processor executes the tasks in the load reduction mode for self-recovering so that the base station apparatus can avoid crashing.

Claims (35)

1 . A self-recovering method of a physical layer of a base station, executed by a processor of a base station apparatus, and comprising steps of:

(a) executing multiple first tasks, one by one, during a time period of one of m time slots in a normal mode in a thread pool;

(b) when finishing executing the first tasks, recording first statuses of the first tasks into a task status vector table, wherein the task status vector table further records second statuses of second tasks of the m time slots other than the one of the m time slots having the first tasks;

(c) when finishing recording the first statuses of the first tasks, determining whether all of the second statuses of the second tasks of a previous k th time slot of the m time slots recorded in the task status vector table are executed statuses;

when the second statuses of the second tasks of the previous k th time slot recorded in the task status vector table are all executed statuses, returning to the step (a); and

when any one of the second statuses of the second tasks of the previous k th time slot recorded in the task status vector table is not the executed status, executing at least one of the second tasks of the previous k th time slot having an unexecuted status within next p consecutive time slots in a load reduction mode, and returning to the step (a);

wherein the at least one of the second tasks of the previous k th time slot having the unexecuted status in the thread pool is executed in a same thread pool within the next p consecutive time slots;

wherein m, k, and p are positive integers;

wherein p+k≤m;

wherein the base station apparatus is a cell site for communicating with mobile devices;

wherein p is determined according to the statuses of the second tasks of the previous k th time slot recorded in the task status vector table; and

wherein the smaller a number of the executed statuses of the second tasks of the previous k th time slot recorded in the task status vector table is, the greater p is.

2 . The self-recovering method as claimed in claim 1 , wherein the task status vector table is stored in a memory of the base station apparatus.

3 . The self-recovering method as claimed in claim 1 , wherein when the processor is in the load reduction mode, a workload for processing subsequent tasks within the next p consecutive time slots is reduced.

4 . The self-recovering method as claimed in claim 3 , wherein when the workload of the processor is reduced, the processor executes i said subsequent tasks within each of the next p consecutive time slots in the load reduction mode;

wherein i is a positive integer, and i≤n; and

wherein n is a number of the first tasks.

5 . A base station apparatus, and comprising:

a memory, storing a task status vector table;

a processor, electrically connected to the memory, and executing steps of:

(a) executing multiple first tasks, one by one, during a time period of one of m time slots in a normal mode in a thread pool;

(b) when finishing executing the first tasks, recording first statuses of the first tasks into a task status vector table, wherein the task status vector table further records second statuses of second tasks of the m time slots other than the one of the m time slots having the first tasks;

(c) when finishing recording the first statuses of the first tasks, determining whether all of the second statuses of the second tasks of a previous k th time slot of the m time slots recorded in the task status vector table are executed statuses;

when the second statuses of the second tasks of the previous k th time slot recorded in the task status vector table are all executed statuses, returning to the step (a); and

when any one of the second statuses of the second tasks of the previous k th time slot recorded in the task status vector table is not the executed status, executing at least one of the second tasks of the previous k th time slot having an unexecuted status within next p consecutive time slots in a load reduction mode, and returning to the step (a);

wherein the at least one of the second tasks of the previous k th time slot having the unexecuted status in the thread pool is executed in a same thread pool within the next p consecutive time slots;

wherein m, k, and p are positive integers;

wherein p+k≤m;

wherein the base station apparatus is a cell site for communicating with mobile devices;

wherein p is determined according to the statuses of the second tasks of the previous k th time slot recorded in the task status vector table; and

wherein the smaller a number of the executed statuses of the second tasks of the previous k th time slot recorded in the task status vector table is, the greater p is.

6 . The base station apparatus as claimed in claim 5 , wherein when the processor is in the load reduction mode, a workload for processing subsequent tasks within the next p consecutive time slots is reduced.

7 . The base station apparatus as claimed in claim 6 , wherein when the workload of the processor is reduced, the processor executes i said subsequent tasks within each of the next p consecutive time slots in the load reduction mode;

wherein i is a positive integer, and i≤n; and

wherein n is a number of the first tasks.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2025
From: AESPULA TECHNOLOGY INC.
To: ALPHA NETWORKS INC.
Reel/Frame 072602/0543 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2023
From: HSU, TERNG-YIN; LIAO, YUAN-TE; KOH, SHUNG-MEI
To: AESPULA TECHNOLOGY INC.
Reel/Frame 062612/0548 →
Continuity (1)
Related Publication 20240264876A1 · Aug 8, 2024
References Cited (19)
US 10552215B1 · Xu · 2020 [cited by examiner]
US 20040187120A1 · Moore · 2004 [cited by examiner]
US 20050283785A1 · D'Souza · 2005 [cited by examiner]
US 20070050779A1 · Hayashi · 2007 [cited by examiner]
US 20080066072A1 · Yurekli · 2008 [cited by examiner]
US 20100083265A1 · Booton · 2010 [cited by examiner]
US 20140196045A1 · Kurata · 2014 [cited by examiner]
US 20140373023A1 · Arakawa · 2014 [cited by examiner]
US 20150026699A1 · Nakamura · 2015 [cited by examiner]
US 20150135185A1 · Sirota · 2015 [cited by examiner]
US 20160055032A1 · David · 2016 [cited by examiner]
US 20180182059A1 · Achiwa · 2018 [cited by examiner]
US 20190129993A1 · Stanfill · 2019 [cited by examiner]
US 20190310892A1 · Frolikov · 2019 [cited by examiner]
US 20200201636A1 · Alexander · 2020 [cited by examiner]
US 20230161629A1 · Saja · 2023 [cited by examiner]
US 20240223344A1 · Huang · 2024 [cited by examiner]
US 20240370075A1 · Subramanian · 2024 [cited by examiner]
CN 103118359A · 2013 [cited by applicant]