Semiconductor package enabling reduction in semiconductor package size
View Patent ↗A semiconductor package includes a substrate, a semiconductor device, and a stiffener. The substrate has a top surface and a bottom surface. The semiconductor device is disposed on the top surface of the substrate. The stiffener is disposed on the bottom surface of the substrate. The stiffener may be disposed on a perimeter portion of the bottom surface of the substrate, and may not be disposed on a central portion of the bottom surface of the substrate. One or more connection components may disposed on the central portion of the bottom surface of the substrate, and a thickness of the stiffener may be greater than or equal to a thickness of the one or more connection components.
1 . A semiconductor package, comprising:
a substrate having a top surface and a bottom surface;
a semiconductor device disposed on the top surface of the substrate;
a stiffener disposed on a perimeter portion of the bottom surface of the substrate, and not disposed on a central portion of the bottom surface of the substrate; and
one or more connection components disposed on the central portion of the bottom surface of the substrate,
wherein a thickness of the stiffener is greater than or equal to a thickness of the one or more connection components.
2 . The semiconductor package of claim 1 ,
wherein the substrate further has a side surface,
wherein a first portion of the stiffener is disposed on the perimeter portion of the bottom surface of the substrate and a second portion of the stiffener is disposed on the side surface of the substrate.
3 . The semiconductor package of claim 1 ,
wherein the thickness of the stiffener is greater than or equal to 76% of the thickness of the one or more connection components.
4 . The semiconductor package of claim 1 ,
wherein the semiconductor package has a width that is greater than a width of the substrate.
5 . The semiconductor package of claim 1 ,
wherein the semiconductor package has a length that is greater than a length of the substrate.
6 . The semiconductor package of claim 1 ,
wherein the stiffener comprises a material with a coefficient of thermal expansion that is less than or equal to 15 parts per million per Celsius degree.
7 . The semiconductor package of claim 1 ,
wherein the semiconductor device comprises an application-specific integrated circuit (ASIC).
8 . A semiconductor package, comprising:
a substrate having a top surface and a bottom surface;
a semiconductor device disposed on the top surface of the substrate; and
a stiffener having a top surface, a bottom surface, and an opening extending through the top surface and the bottom surface of the stiffener, and
wherein the top surface of the stiffener is disposed on the bottom surface of the substrate, and
wherein a footprint of the stiffener is greater than a footprint of the substrate.
9 . The semiconductor package of claim 8 ,
wherein the top surface of the stiffener is not disposed on a portion of the bottom surface of the substrate that is associated with a portion of the top surface of the substrate on which the semiconductor device is disposed.
10 . The semiconductor package of claim 8 ,
wherein the substrate further has a side surface,
wherein a portion of the stiffener is disposed on the side surface of the substrate.
11 . The semiconductor package of claim 8 ,
wherein the stiffener has a thickness that is greater than or equal to a thickness of one or more connection components disposed on a portion of the bottom surface of the substrate upon which the stiffener is not disposed.
12 . The semiconductor package of claim 8 ,
wherein the stiffener has a frame width that is greater than or equal to 2 millimeters (mm) and less than or equal to 20 mm.
13 . The semiconductor package of claim 8 ,
wherein the stiffener has a frame length that is greater than or equal to 2 millimeters (mm) and less than or equal to 20 mm.
14 . The semiconductor package of claim 8 ,
wherein the stiffener comprises a material with a coefficient of thermal expansion that is less than or equal to 15 parts per million per Celsius degree.
15 . The semiconductor package of claim 8 ,
wherein the stiffener is configured to cause warpage of the semiconductor package, during operation of the semiconductor package, to be less than or equal to 300 micrometers.
16 . A semiconductor package, comprising:
a substrate having a top surface and a bottom surface;
a semiconductor device disposed on the top surface of the substrate; and
a stiffener disposed on a first portion of the bottom surface of the substrate,
wherein a thickness of the stiffener is greater than or equal to a thickness of one or more connection components disposed on a second portion of the bottom surface of the substrate, and
wherein a footprint of the stiffener is greater than a footprint of the substrate.
17 . The semiconductor package of claim 16 ,
wherein the stiffener is not disposed on the second portion of the bottom surface of the substrate.
18 . The semiconductor package of claim 16 ,
wherein the substrate further has a side surface,
wherein a portion of the stiffener is disposed on the side surface of the substrate.
19 . The semiconductor package of claim 16 , wherein a difference between a length of the substrate and a length of the stiffener is less than or equal to a threshold.
20 . The semiconductor package of claim 16 , wherein the first portion is a perimeter portion.