Mediating directed refresh management induced row hammer and row access strobe (RAS) clobber failures
There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.
1. A memory device comprising:
at least one memory including a plurality of memory cells disposed in rows and columns; and
a controller, communicatively coupled to the at least one memory, the controller maintaining data integrity in the at least one memory by executing operations comprising:
receiving an indication that a row hammer threshold (RHT) has been exceeded;
issuing a first directed refresh management (DRFM) command;
triggering an activation command (ACT) for at least one victim row counter, the at least one victim row counter being associated with at least one row affected by a row hammer event;
executing a base protocol to mitigate the row hammer event;
adding a DRFM mitigation protocol to a queue for execution in response to a new DRFM command being triggered;
determining a most recent victim row of the new DRFM command; and
issuing the first DRFM command if the queue is empty.
2. The memory device of claim 1 , wherein the memory device comprises a DRAM.
3. The memory device of claim 1 , wherein the base protocol includes a probabilistic protocol configured to mitigate a native risk of failure of the memory.
4. The memory device of claim 1 , wherein when controller is configured to mitigate a RH 1 risk (+/1 rows), a RH 2 risk (+/−2 rows), and a RAS clobber risk as risk of failure of the memory.
5. The memory device of claim 2 , wherein the base protocol includes at least one of a RH refresh (RHR) protocol, an address sampling (AS) protocol, and a content addressable memory (CAM) protocol.
6. The memory device of claim 2 , wherein the base protocol includes an activity tracking (AT) protocol.
7. The memory device of claim 1 , wherein the base protocol further includes a native deterministic RH risk mitigation protocol.
8. The memory device of claim 7 , wherein the native deterministic RH risk mitigation protocol is based on a DRFM servicing protocol.
9. The memory device of claim 1 , wherein the base protocol includes at least one of a space saving (SS) RH protocol, a Revised Misra-Grise RH protocol, and a lockout SS RH protocol.
10. The memory device of claim 1 , wherein the base protocol includes a Ping-Pong protocol.
11. A method for mitigating risk of failure in a memory device including at least one memory, the method comprising:
executing, by a controller configured to maintain data integrity in the at least one, operations comprising:
receiving an indication that a Row Hammer Threshold (RHT) has been exceeded;
issuing a first directed refresh management (DRFM) command;
triggering an activation command (ACT) for at least one victim row counter, the at least one victim row counter being associated with at least one row affected by a row hammer event;
executing a base protocol to mitigate the row hammer event;
adding a DRFM mitigation protocol to a queue for execution in response to a new DRFM command being triggered; and
determining a most recent victim row of the new DRFM command and if the queue is empty, issuing the first DRFM command.
12. The method of claim 11 , wherein the memory device comprises a DRAM.
13. The method of claim 11 , wherein the operations further include: executing the base protocol to mitigate a risk of failure selected from the set of failure risks consisting of a Row Hammer (RH) failure risk, and a RAS Clobber failure risk.
14. The method of claim 13 , wherein when the failure risk is a RH failure risk, the deterministic protocol is configured to mitigate a RH1 risk (+/1 rows), a RH2 risk (+/−2 rows), a RAS clobber risk, and an inverse hammer risk.
15. The method of claim 14 , wherein the inverse hammer risk is a DRFM-induced RH failure risk consisting of a RH/3/4 (+/−3, 4) risk.
16. The method of claim 13 , wherein the base protocol includes at least one of a RH refresh (RHR) protocol, an address sampling (AS) protocol, and a content addressable memory (CAM) protocol.
17. The method of claim 13 , wherein the base protocol includes an activity tracking (AT) protocol.
18. The method of claim 11 , wherein the base protocol includes further includes a native deterministic RH risk mitigation protocol; and
wherein the controller is configured is configured to mitigate failure risks deterministically.
19. The method of claim 13 , wherein the controller is configured is configured to mitigate failure risks deterministically in conjunction with addressing native failure risks using a probabilistic mitigation protocol.
20. A non-transitory computer readable medium having stored thereon computer executable instructions that, if executed by a computing device, cause the computing device to perform a method for mitigating risk of failure in a memory device including at least one memory, the method comprising:
executing, by a controller configured to maintain data integrity in the at least one, operations comprising:
receiving an indication that a Row Hammer Threshold (RHT) has been exceeded;
issuing a first directed refresh management (DRFM) command;
triggering an activation command (ACT) for at least one victim row counter, the at least one victim row counter being associated with at least one row affected by a row hammer event;
executing a base protocol to mitigate the row hammer event; adding a DRFM mitigation protocol to a queue for execution in response to a new DRFM command being triggered; and
determining a most recent victim row of the new DRFM command and if the queue is empty, issuing the first DRFM command.