Bit line sense amplifier and bit line sensing method of semiconductor memory device
View Patent ↗A bit line sense amplifier includes: a first inverter configured to receive an input signal from a bit line via an input terminal and output a first signal to a first node; a second inverter configured to receive the first signal and output a second signal to a second node; a differential amplifier configured to receive the input signal as a positive input, and receive the second signal as a negative input; and a first switch configured to electrically connect the input terminal to the positive input of the differential amplifier and a second switch configured to electrically connect the second node to the negative input of the differential amplifier.
1. A bit line sense amplifier comprising:
a first inverter configured to receive an input signal from a bit line via an input terminal and configured to output a first signal to a first node;
a second inverter configured to receive the first signal and configured to output a second signal to a second node;
a differential amplifier configured to receive the input signal as a positive input, and receive the second signal as a negative input;
a first switch configured to electrically connect the input terminal to the positive input of the differential amplifier; and
a second switch configured to electrically connect the second node to the negative input of the differential amplifier,
wherein the first inverter is electrically connected to the second inverter through a first current source that is configured to provide a pull-up current to the first signal and a second current source that is configured to provide a pull-down current to the first signal.
2. The bit line sense amplifier of claim 1 , wherein the first current source and the second current source each comprise a dependent current source, and
the first current source is configured to adjust the first signal based on the input signal, and the second current source is configured to adjust the first signal based on an output signal of the differential amplifier.
3. The bit line sense amplifier of claim 1 , wherein the first current source and the second current source each comprise a dependent current source, and
the first current source is configured to adjust the first signal based on an output signal of the differential amplifier, and the second current source is configured to adjust the first signal based on the input signal.
4. The bit line sense amplifier of claim 1 , wherein the first current source comprises an independent current source, and the second current source comprises a dependent current source, and
the second current source is configured to adjust the first signal based on an output signal of the differential amplifier.
5. The bit line sense amplifier of claim 1 , wherein the first current source comprises a dependent current source, and the second current source comprises an independent current source, and
the first current source is configured to adjust the first signal based on an output signal of the differential amplifier.
6. The bit line sense amplifier of claim 1 , wherein, when the first switch and the second switch are closed, an output signal of the second current source is configured to be adjusted based on an output signal of the differential amplifier, and the second signal is configured to be adjusted based on the output signal of the second current source.
7. The bit line sense amplifier of claim 1 , further comprising a third switch electrically connecting the second node and the input terminal.
8. The bit line sense amplifier of claim 7 , wherein, the bit line sense amplifier is configured to perform a bit line sensing operation based on the input signal when the first switch, the second switch, and the third switch are open.
9. The bit line sense amplifier of claim 7 , wherein the bit line sense amplifier is configured to perform a restoration operation of a memory cell when the first switch and the second switch are open, and the third switch is closed.
10. A bit line sensing method performed by a bit line sense amplifier, the bit line sensing method comprising:
inputting an input signal via an input terminal of the bit line sense amplifier;
outputting a first signal to a first node using a first inverter when the input signal is input to the first inverter;
outputting a second signal to a second node using a second inverter after the first signal is input to the second inverter; and
inputting the input signal as a positive input and inputting the second signal as a negative input to a differential amplifier;
wherein the first signal is adjusted by a first current source that is configured to provide a pull-up current to the first signal and a second current source that is configured to provide a pull-down current to the first signal.
11. The bit line sensing method of claim 10 , wherein the first current source and the second current source each comprise a dependent current source, and
the first current source is configured to adjust the first signal based on the input signal, and the second current source is configured to adjust the first signal based on an output signal of the differential amplifier.
12. The bit line sensing method of claim 10 , wherein the first current source and the second current source each comprise a dependent current source, and
the first current source is configured to adjust the first signal based on an output signal of the differential amplifier, and the second current source is configured to adjust the first signal based on the input signal.
13. The bit line sensing method of claim 10 , wherein the first current source comprises an independent current source, and the second current source comprises a dependent current source, and
the second current source is configured to adjust the first signal based on an output signal of the differential amplifier.
14. The bit line sensing method of claim 10 , wherein the first current source comprises a dependent current source, and the second current source comprises an independent current source, and
the first current source is configured to adjust the first signal based on an output signal of the differential amplifier.
15. The bit line sensing method of claim 10 , wherein, the bit line sense amplifier further comprises a first switch electrically connecting the input terminal and the differential amplifier, and a second switch electrically connecting the second node and the differential amplifier, and
wherein, when the first switch and the second switch are closed, an output of the second current source is adjusted based on an output of the differential amplifier, and the second signal is adjusted based on the output of the second current source.
16. The bit line sensing method of claim 10 , wherein the bit line sense amplifier further comprises a first switch electrically connecting the input terminal and the differential amplifier, a second switch electrically connecting the second node and the differential amplifier, and a third switch electrically connecting the input terminal and the second node, and
wherein, when the first switch, the second switch, and the third switch are open, a bit line sensing operation is performed based on the input signal.
17. The bit line sensing method of claim 10 , wherein, the bit line sense amplifier further comprises a first switch electrically connecting the input terminal and the differential amplifier, a second switch electrically connecting the second node and the differential amplifier, and a third switch electrically connecting the input terminal and the second node, and
wherein, when the first switch and the second switch are open, and the third switch is closed, a restoration operation of a memory cell is performed.
18. A bit line sense amplifier configured to perform a bit line sensing operation, the bit line sense amplifier comprising:
a first inverter configured to receive an input signal via an input terminal of the first inverter and configured to output a first signal;
a second inverter configured to receive the first signal and configured to output a second signal to a second node;
a differential amplifier configured to receive the input signal as a positive input and configured to receive the second signal as a negative input;
a first switch configured to electrically connect the input terminal of the first inverter and the positive input of the differential amplifier;
a second switch configured to electrically connect the second node and the negative input of the differential amplifier;
a first current source configured to adjust the first signal by providing a pull-up current;
a second current source configured to adjust the first signal by providing a pull-down current; and
a switching unit configured to electrically connect the input terminal of the first inverter and one of a plurality of bit lines.
19. The bit line sense amplifier of claim 18 , wherein the switching unit comprises a first switching block electrically connected to a first memory block not including dummy lines and a second switching block electrically connected to a second memory block including dummy lines.
20. The bit line sense amplifier of claim 19 , wherein the switching unit is configured to close the second switching block, when the input terminal is electrically connected to the second memory block.