Processor-based system for allocating cache lines to a higher-level cache memory

1. A processor-based system for allocating a cache line to a higher-level cache memory, comprising:

a lower-level cache memory configured to store data;

the processor-based system configured to, in response to an eviction request of a lower-level cache line in the lower-level cache memory:

determine whether the lower-level cache line is opportunistic;

set an opportunistic indicator to indicate whether the lower-level cache line is opportunistic;

communicate the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory;

determine, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line; and

in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:

replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

2. The processor-based system of claim 1 , configured to determine whether the higher-level cache line of the plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line by being configured to:

determine whether the higher-level cache line in the higher-level cache memory is invalid; and

in response to the determining the higher-level cache line in the higher-level cache memory is invalid:

replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

3. The processor-based system of claim 2 , further configured, in response to determining whether the higher-level cache line in the higher-level cache memory is not invalid, by being configured to:

determine based on a second opportunistic indicator of the higher-level cache line whether the higher-level cache line in the higher-level cache memory is opportunistic; and

in response to the determining the second opportunistic indicator of the higher-level cache line is opportunistic:

replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

4. The processor-based system of claim 3 , further configured, in response to determining whether the higher-level cache line in the higher-level cache memory is not opportunistic, to:

determine based on a dirty indicator of the lower-level cache line whether the lower-level cache line is dirty; and

in response to the determining the dirty indicator of the lower-level cache line is dirty:

write the lower-level cache line to a system memory.

5. The processor-based system of claim 1 , wherein the opportunistic indicator indicates that the lower-level cache line is opportunistic.

6. The processor-based system of claim 1 , configured to determine whether the higher-level cache line in the higher-level cache memory has less or equal importance than the lower-level cache line by being configured to:

determine if a first higher-level cache line has less or equal importance than the lower-level cache line;

determine if a second higher-level cache line has less or equal importance than the lower-level cache line; and

in response to determining the first higher-level cache line has less or equal importance than the lower-level cache line and the second higher-level cache line has less or equal importance than the lower-level cache line:

determine if the first higher-level cache line has less or equal importance than the second higher-level cache line; and

in response to determining that the first higher-level cache line has less or equal importance than the second higher-level cache line:

replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line, and

associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

7. The processor-based system of claim 6 , configured to determine if the first higher-level cache line has less or equal importance than the second higher-level cache line by being configured to:

determine if the first higher-level cache line is invalid;

determine if the second higher-level cache line is not invalid; and

in response to determining that the first higher-level cache line is invalid and the second higher-level cache line is not invalid:

replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

8. The processor-based system of claim 7 , further configured, in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, by being configured to:

determine a first priority indicator of the first higher-level cache line and a second priority indicator of the second higher-level cache line; and

in response to determining that the first priority indicator of the first higher-level cache line is less recently used than the second priority indicator of the second higher-level cache line:

replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

9. The processor-based system of claim 7 , further configured, in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, by being configured to:

determine a LRU indicator tracking an order of a plurality of least recently used cache lines, including the first higher-level cache line and the second higher-level cache line; and

in response to determining that the LRU indicator indicates the first higher-level cache line is less recently used than the second higher-level cache line:

replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

10. The processor-based system of claim 1 , configured to associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory by being configured to:

store the opportunistic indicator of the lower-level cache line with the higher-level cache line.

11. The processor-based system of claim 1 integrated into an integrated circuit (IC).

12. The processor-based system of claim 1 integrated into a device selected from a group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.

13. A processor-based system for allocating a cache line to a higher-level cache memory in response to an eviction request of a lower-level cache line in a lower-level cache memory, comprising:

means for determining whether the lower-level cache line is opportunistic;

means for setting an opportunistic indicator to indicate whether the lower-level cache line is opportunistic;

means for communicating the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory;

means for determining, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line; and

in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:

means for replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

means for associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

14. A method for allocating a cache line to a higher-level cache memory in response to an eviction request of a lower-level cache line in a lower-level cache memory, comprising:

determining whether the lower-level cache line is opportunistic;

setting an opportunistic indicator to indicate whether the lower-level cache line is opportunistic;

communicating the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory;

determining, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line; and

in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:

replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

15. The method of claim 14 , wherein determining whether the higher-level cache line of the plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line comprises:

determining whether the higher-level cache line in the higher-level cache memory is invalid; and

in response to the determining the higher-level cache line in the higher-level cache memory is invalid:

replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

16. The method of claim 15 , wherein, in response to determining whether the higher-level cache line in the higher-level cache memory is not invalid, further comprising:

determining based on a second opportunistic indicator of the higher-level cache line whether the higher-level cache line in the higher-level cache memory is opportunistic; and

in response to the determining the second opportunistic indicator of the higher-level cache line is opportunistic:

replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

17. The method of claim 16 , wherein, in response to determining whether the higher-level cache line in the higher-level cache memory is not opportunistic, comprising:

determining based on a dirty indicator of the lower-level cache line whether the lower-level cache line is dirty; and

in response to the determining the dirty indicator of the lower-level cache line is dirty:

writing the lower-level cache line to a system memory.

18. The method of claim 14 , wherein the opportunistic indicator indicates that the lower-level cache line is opportunistic.

19. The method of claim 14 , wherein determining whether the higher-level cache line in the higher-level cache memory has less or equal importance than the lower-level cache line further comprises:

determining if a first higher-level cache line has less or equal importance than the lower-level cache line;

determining if a second higher-level cache line has less or equal importance than the lower-level cache line; and

in response to determining the first higher-level cache line has less or equal importance than the lower-level cache line and the second higher-level cache line has less or equal importance than the lower-level cache line:

determining if the first higher-level cache line has less or equal importance than the second higher-level cache line; and

in response to determining that the first higher-level cache line has less or equal importance than the second higher-level cache line:

replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

20. The method of claim 19 , wherein determining if the first higher-level cache line has less or equal importance than the second higher-level cache line further comprises:

determining if the first higher-level cache line is invalid;

determining if the second higher-level cache line is invalid; and

in response to determining that the first higher-level cache line is invalid and the second higher-level cache line is not invalid:

replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

21. The method of claim 20 , wherein, in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, further comprising:

determining a first priority indicator of the first higher-level cache line and a second priority indicator of the second higher-level cache line; and

in response to determining that the first priority indicator of the first higher-level cache line is less recently used than the second priority indicator of the second higher-level cache line:

replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

22. The method of claim 20 , wherein, in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, comprising:

determining a LRU indicator tracking an order of a plurality of least recently used cache lines, including the first higher-level cache line and the second higher-level cache line; and

in response to determining that the LRU indicator indicates the first higher-level cache line is less recently used than the second higher-level cache line:

replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.