IP Library › Granted Patent US 12,381,632
Granted Patent B2
US 12,381,632 · App. 18/170,326 · Granted Aug 5, 2025

Waveguide delay based equalization with current summing in a differential transimpedance amplifier

Inventors: Simon S. Pang (San Diego, CA); Wei Li (San Diego, CA)
Assignee: Cisco Technology, Inc.
H04B10/6971H04B10/612
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,381,632
App. No.
18/170,326
Granted
Aug 5, 2025
Kind
B2
Abstract

A waveguide delay-based equalization (WDEQ) system is described. The WDEQ system provides a delay in waveguides of the system and electrical signal summing in a differential transimpedance amplifier (TIA) which increases the performance (e.g., bandwidth, etc.) of the optical receiver. The WDEQ system includes an optoelectronic circuit with a directional coupler, a first photodetector, at least two transistors connected to the first photodetector, an optical delay, and a differential transimpedance amplifier (TIA).

Claims (51)

1. A method comprising:

receiving an input optical signal;

splitting the input optical signal into a first optical signal and a second optical signal;

delaying the first optical signal;

converting the delayed first optical signal to a first electrical signal using a first photodetector and at least two transistors connected to the first photodetector;

converting the second optical signal to a second electrical signal using a second photodetector and at least two transistors connected to the second photodetector and a differential transimpedance amplifier (TIA); and

summing the first and second electrical signals using the differential TIA.

2. The method according to claim 1 , comprising delaying the first optical signal using a waveguide delay.

3. The method according to claim 2 , wherein the waveguide delay is coupled to an output of a directional coupler.

4. The method according to claim 1 , wherein the first photodetector comprises a first photodiode, wherein the at least two transistors connected to the first photodetector comprise a first NMOS transistor and a first PMOS transistor, and wherein the second photodetector comprises a second photodiode to convert the second optical signal to the second electrical signal, wherein the at least two transistors connected to the second photodetector comprise a second NMOS transistor and a second PMOS transistor.

5. The method according to claim 4 , wherein:

an anode from the first photodiode is connected to a first stage of the differential TIA,

a cathode of the first photodiode is connected to a second stage of the differential TIA,

an anode from the second photodiode is connected to the second stage of the differential TIA, and

a cathode of the second photodiode is connected to the first stage of the differential TIA.

6. The method of claim 5 , wherein each connection between the first photodiode and the first stage and the second stage comprises a signal pad and a Metal-Insulator-Metal Capacitor, and wherein each connection between the second photodiode and the first stage and the second stage comprises a signal pad and a Metal-Insulator-Metal Capacitor.

7. The method according to claim 1 , comprising splitting the second optical signal into a third optical signal and a fourth optical signal using a second directional coupler before generating the second electrical signal.

8. The method according to claim 7 , further comprising:

delaying the fourth optical signal; and

coupling the delayed fourth optical signal and the third optical signal to the differential TIA.

9. A system for communication, the system comprising:

an optoelectronic circuit comprising a directional coupler, a first photodetector, at least two transistors connected to the first photodetector, an optical delay, and a differential transimpedance amplifier (TIA), the optoelectronic circuit being operable to:

receive an input optical signal;

split the input optical signal into a first optical signal and a second optical signal via the directional coupler;

delay the first optical signal via the optical delay;

convert the delayed first optical signal to a first electrical signal using the first photodetector;

convert the second optical signal to a second electrical signal using a second photodetector with at least two transistors connected to the second photodetector and the differential TIA; and

sum the first and second electrical signals using the differential TIA.

10. The system of claim 9 , wherein the optical delay comprises a waveguide delay.

11. The system of claim 10 , wherein the waveguide delay is coupled to an output of the directional coupler.

12. The system of claim 10 , wherein the first photodetector comprises a first photodiode, wherein the at least two transistors connected to the first photodetector comprise a first NMOS transistor and a first PMOS transistor, and wherein the second photodetector comprises a second photodiode to convert the second optical signal to the second electrical signal, wherein the at least two transistors connected to the second photodetector comprise a second NMOS transistor and a second PMOS transistor.

13. The system of claim 12 , wherein:

an anode from the first photodiode is connected to a first stage of the differential TIA,

a cathode of the first photodiode is connected to a second stage of the differential TIA,

an anode from the second photodiode is connected to the second stage of the differential TIA, and

a cathode of the second photodiode is connected to the first stage of the differential TIA.

14. The system of claim 13 , wherein each connection between the first photodiode and the first stage and the second stage comprises a signal pad and a Metal-Insulator-Metal Capacitor, and wherein each connection between the second photodiode and the first stage and the second stage comprises a signal pad and a Metal-Insulator-Metal Capacitor.

15. The system of claim 9 , the optoelectronic circuit being further operable to:

split the second optical signal into a third optical signal and a fourth optical signal using a second directional coupler before generating the second electrical signal.

16. The system of claim 15 , the optoelectronic circuit being further operable to:

delay the fourth optical signal via a second optical delay; and

wherein the delayed fourth optical signal and the third optical signal are coupled to the differential TIA.

17. A method comprising:

receiving an input optical signal;

splitting the input optical signal into a first optical signal and a second optical signal;

converting the first optical signal to a first electrical signal using a first photodetector with at least two transistors connected to the first photodetector;

converting the second optical signal to a second electrical signal using a second photodetector with at least two transistors connected to the second photodetector and a differential transimpedance amplifier (TIA); and

summing the first and second electrical signals using the differential TIA.

18. The method according to claim 17 , wherein the first photodetector is coupled to an output of a directional coupler.

19. The method according to claim 17 , wherein the first photodetector comprises a first photodiode, wherein the at least two transistors connected to the first photodetector comprise a first NMOS transistor and a first PMOS transistor, and wherein the second photodetector comprises a second photodiode to convert the second optical signal to the second electrical signal, wherein the at least two transistors connected to the second photodetector comprise a second NMOS transistor and a second PMOS transistor.

20. The method according to claim 17 , wherein an anode from the first photodetector is connected to a first stage of the differential TIA, and a cathode of the first photodetector is connected to a second stage of the differential TIA.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2023
From: PANG, SIMON S.; LI, WEI
To: CISCO TECHNOLOGY, INC.
Reel/Frame 062724/0569 →
Continuity (2)
Provisional Application 63378608 · Oct 6, 2022
Related Publication 20240121009A1 · Apr 11, 2024
References Cited (15)
US 5331452A · Smyth · 1994 [cited by examiner]
US 11323185B2 · Pang et al. · 2022 [cited by applicant]
US 20080219680A1 · Omori · 2008 [cited by examiner]
US 20130028596A1 · Suzuki · 2013 [cited by examiner]
US 20140205300A1 · Hemenway, Jr. · 2014 [cited by examiner]
US 20150311982A1 · Georgas et al. · 2015 [cited by applicant]
US 20170093349A1 · Elliott · 2017 [cited by examiner]
US 20180006731A1 · Pang · 2018 [cited by examiner]
US 20180292682A1 · Dupuis et al. · 2018 [cited by applicant]
US 20190049666A1 · Welch · 2019 [cited by applicant]
US 20190052370A1 · Pang · 2019 [cited by examiner]
US 20190212496A1 · Karimelahi et al. · 2019 [cited by applicant]
US 20200014566A1 · Ahmed et al. · 2020 [cited by applicant]
US 20200162170A1 · Pang · 2020 [cited by examiner]
US 20210126594A1 · Lambrecht et al. · 2021 [cited by applicant]