IP Library › Granted Patent US 12,537,486
Granted Patent B2
US 12,537,486 · App. 18/170,390 · Granted Jan 27, 2026

Amplifier with output harmonic termination and output impedance network

Inventors: Yunfei Wang (Chengdu, CN); Tong Qiao (Chengdu, CN); Hongyu Xiang (Chengdu, CN)
Assignee: NXP USA, Inc.
H03F3/193H03F1/086H03F1/565H03F2200/222H03F2200/451
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Quick Facts
Patent No.
US 12,537,486
App. No.
18/170,390
Granted
Jan 27, 2026
Kind
B2
Abstract

An amplifier device may include an amplifier transistor and having harmonic termination circuitry and an output impedance network, such as an output T network, coupled to the output of the amplifier transistor. The amplifier device may be configured as an inverted F class amplifier having an operational frequency range with a center frequency of less than or equal to around 2.6 GHz. The harmonic termination circuitry and output impedance network may be configured to create a short circuit or near short circuit at the amplifier transistor output for third harmonic frequencies of the center frequency of the amplifier transistor and to create an open circuit or near open circuit at the amplifier transistor output for second harmonic frequencies of the center frequency. The output impedance network may be configured to increase the output impedance at the center frequency and reduce signal loss for the amplifier device.

Claims (59)

1 . An amplifier device comprising:

a transistor having a first current terminal, a second current terminal, and a control terminal;

an input coupled to the control terminal of the transistor;

an output coupled to the first current terminal of the transistor;

a reference potential coupled to the second current terminal of the transistor;

at least one harmonic termination circuit coupled to the first current terminal of the transistor; and

an impedance network comprising:

a first inductor coupled between the first current terminal of the transistor and an intermediate node;

a second inductor coupled between the output and the intermediate node; and

a capacitor coupled between the intermediate node and the reference potential, wherein the at least one harmonic termination circuit comprises:

a second harmonic termination circuit comprising:

a first terminal coupled between the second inductor of the impedance network and the output;

a second terminal coupled to the reference potential; and

a series LC circuit coupled between the first terminal and the second terminal, wherein the second harmonic termination circuit is configured to have a resonance corresponding to a second harmonic of a center frequency of the amplifier device.

2 . The amplifier device of claim 1 , wherein the at least one harmonic termination circuit comprises:

a third harmonic termination circuit comprising:

a third terminal coupled between the first inductor of the impedance network and first current terminal of the transistor;

a fourth terminal coupled to the reference potential; and

a series LC circuit coupled between the third terminal and the fourth terminal, wherein the third harmonic termination circuit is configured to have a resonance corresponding to a third harmonic of the center frequency of the amplifier device.

3 . The amplifier device of claim 1 , wherein the first inductor includes a first bond wire and the second inductor includes a second bond wire.

4 . The amplifier device of claim 1 , wherein a center frequency of the amplifier device is less than or equal to 2.6 GHz.

5 . The amplifier device of claim 1 , wherein the amplifier device is configured as an inverse class F amplifier device.

6 . The amplifier device of claim 1 , further comprising:

an input harmonic termination circuit coupled to the control terminal of the transistor, wherein the input harmonic termination circuit is configured to have a resonance corresponding to a second harmonic of a center frequency of the amplifier device.

7 . An amplifier package comprising:

an active die comprising an amplifier transistor having a gate terminal, a source terminal, and a drain terminal;

a first integrated passive device (IPD) die comprising a first plurality of capacitors and being coupled to the gate terminal via at least a first bond wire;

a second IPD die comprising a second plurality of capacitors and being coupled to the drain terminal via at least a second bond wire and a third bond wire;

an output conductor coupled to the second IPD die via at least a fourth bond wire and a fifth bond wire;

a second harmonic termination circuit comprising the fourth bond wire and a first capacitor of the second plurality of capacitors disposed in the second IPD die; and

an impedance network having a T configuration, the impedance network comprising the second bond wire, the fifth bond wire, and a second capacitor of the second plurality of capacitors of the second IPD die.

8 . The amplifier package of claim 7 , wherein the second harmonic termination circuit has a resonance corresponding to a second harmonic of a center frequency of the amplifier transistor.

9 . The amplifier package of claim 8 , further comprising:

a third harmonic termination circuit comprising the third bond wire and a third capacitor of the second plurality of capacitors of the second IPD die, wherein the third harmonic termination circuit has a resonance corresponding to a third harmonic of the center frequency of the amplifier transistor.

10 . The amplifier package of claim 9 , further comprising:

a reference plane, wherein the first capacitor, the second capacitor, and the third capacitor of the second plurality of capacitors of the second IPD die are coupled to the reference plane.

11 . The amplifier package of claim 10 , further comprising:

an input harmonic termination circuit that includes the first bond wire and a first capacitor of the first plurality of capacitors of the first IPD die, wherein the first capacitor of the first plurality of capacitors of the first IPD die is coupled to the reference plane, and the input harmonic termination circuit has a resonance corresponding to the second harmonic of the center frequency of the amplifier transistor.

12 . An amplifier device comprising:

a transistor, the transistor having a gate terminal, a drain terminal, and a source terminal;

an input coupled to the gate terminal of the transistor;

an output coupled to the drain terminal of the transistor;

a reference potential coupled to the source terminal of the transistor;

at least one harmonic termination circuit coupled to the drain terminal of the transistor; and

an impedance network having a T configuration coupled between the drain terminal of the transistor and the output, wherein the impedance network comprises a first inductor coupled between the drain terminal of the transistor and an intermediate node, a second inductor coupled between the output and the intermediate node, and a capacitor coupled between the intermediate node and the reference potential, and wherein the at least one harmonic termination circuit comprises:

a second harmonic termination circuit comprising:

a first terminal coupled between the second inductor of the impedance network and the output;

a second terminal coupled to the reference potential; and

a series LC circuit coupled between the first terminal and the second terminal, wherein the second harmonic termination circuit is configured to have a resonance corresponding to a second harmonic of a center frequency of the amplifier device.

13 . The amplifier device of claim 12 , wherein the at least one harmonic termination circuit comprises:

a third harmonic termination circuit comprising:

a third terminal coupled between the first inductor of the impedance network and drain terminal of the transistor;

a fourth terminal coupled to the reference potential; and

a series LC circuit coupled between the third terminal and the fourth terminal, wherein the third harmonic termination circuit is configured to have a resonance corresponding to a third harmonic of the center frequency of the amplifier device.

14 . The amplifier device of claim 12 , wherein the first inductor and the second inductor are bond wires.

15 . The amplifier device of claim 12 , wherein a center frequency of the amplifier device is less than or equal to 2.6 GHz.

16 . The amplifier device of claim 12 , wherein the amplifier device is configured as an inverse class F amplifier device.

17 . The amplifier device of claim 12 , further comprising:

an input harmonic termination circuit coupled to the gate terminal of the transistor, wherein the input harmonic termination circuit is configured to have a resonance corresponding to a second harmonic of a center frequency of the amplifier device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2023
From: WANG, YUNFEI; QIAO, TONG; XIANG, HONGYU
To: NXP USA, INC.
Reel/Frame 062725/0498 →
Priority Claims (1)
CN 202211524477.0 · Nov 30, 2022 · national
Continuity (1)
Related Publication 20240178803A1 · May 30, 2024
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