IP Library › Granted Patent US 12,439,620
Granted Patent B2
US 12,439,620 · App. 18/172,426 · Granted Oct 7, 2025

Semiconductor device

Inventors: Shin Takizawa (Kariya, JP); Yusuke Nonaka (Kariya, JP); Kenta Gouda (Kariya, JP); Shunsuke Harada (Kariya, JP)
Assignee: DENSO CORPORATION
H10D12/038H10D30/668H10D30/669H10D62/127H10D62/152H10D62/393H10D64/117
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Quick Facts
Patent No.
US 12,439,620
App. No.
18/172,426
Granted
Oct 7, 2025
Kind
B2
Abstract

A semiconductor device includes a cell portion and a peripheral portion. The cell portion has a semiconductor element including a drift layer, a first impurity region, a second impurity region, trench-gate structures, a high-concentration layer, an interlayer insulating film, a first electrode and a second electrode. The interlayer insulating film is located on the trench-gate structures, the first impurity region and the second impurity region, and has a first contact hole communicating with the first impurity region and the second impurity region. The peripheral portion has a section facing the cell portion in one direction, and the interlayer insulating film further has a second contact hole at the section of the peripheral portion. The second contact hole exposes the first impurity region, and the first electrode is electrically connected to the first impurity region through the second contact hole in the peripheral portion.

Claims (30)

1. A semiconductor device comprising:

a cell portion having a semiconductor element; and

a peripheral portion surrounding the cell portion, wherein

the semiconductor element in the cell portion includes:

a drift layer being a first conductivity type;

a first impurity region located on the drift layer and being a second conductivity type;

a second impurity region located at a surface layer portion of the first impurity region inside the first impurity region, the second impurity region being the first conductivity type and having a higher impurity concentration than the drift layer;

a plurality of trench-gate structures arranged in a stripe shape, each of the plurality of trench-gate structures including a gate trench, a shield electrode, an intermediate insulating film, a gate electrode, and an insulating film, the gate trench having one direction as a longitudinal direction of the gate trench while penetrating the first impurity region from the second impurity region and reaching the drift layer, each of the plurality of trench-gate structures configured to have double gates by stacking the shield electrode, the intermediate insulating film and the gate electrode in order via the insulating film in the gate trench;

a high-concentration layer being the first conductivity type or the second conductivity type, the high-concentration layer located on a side opposite from the first impurity region with the drift layer sandwiched between the first impurity region and the high-concentration layer;

an interlayer insulating film located on each of the plurality of trench-gate structures, the first impurity region and the second impurity region, the interlayer insulating film having a first contact hole communicating with the first impurity region and the second impurity region;

a first electrode electrically connected to the first impurity region and the second impurity region through the first contact hole; and

a second electrode electrically connected to the high-concentration layer,

the first impurity region extends from the cell portion to the peripheral portion,

the peripheral portion has a section facing the cell portion in the one direction,

the interlayer insulating film further has a second contact hole at the section of the peripheral portion,

the second contact hole exposes the first impurity region, and

the first electrode is electrically connected to the first impurity region through the second contact hole in the peripheral portion.

2. The semiconductor device according to claim 1 , wherein

the semiconductor element in the cell portion further includes:

a contact trench located between adjacent two of the plurality of trench-gate structures, the contact trench having the one direction as a longitudinal direction of the contact trench, the contact trench extending from the cell portion to the peripheral portion while penetrating the second impurity region and reaching the first impurity region; and

a contact region configured for the second impurity region, the contact region located around the contact trench and located along a wall surface of the contact trench, the contact region having a higher impurity concentration than the second impurity region, and

the first contact hole of the interlayer insulating film communicates with the contact trench.

3. The semiconductor device according to claim 1 , wherein

the insulating film includes a gate insulating film located between the gate trench and the gate electrode,

the gate insulating film has a first part located at the peripheral portion and a second part located at the cell portion, and

the first part has a larger thickness than the second part.

4. The semiconductor device according to claim 1 , wherein

the cell portion includes a main cell region and a sense cell region,

the main cell region has a structure identical to the sense cell region, and

the sense cell region is configured to enable a flow of a smaller current than the main cell region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2023
From: TAKIZAWA, SHIN; NONAKA, YUSUKE; GOUDA, KENTA; HARADA, SHUNSUKE
To: DENSO CORPORATION
Reel/Frame 063216/0956 →
Priority Claims (1)
JP 2020-142628 · Aug 26, 2020 · national
Continuity (2)
Continuation PCTJP2021030995 · Aug 24, 2021
Related Publication 20230197845A1 · Jun 22, 2023
References Cited (4)
US 20100123187A1 · Burke · 2010 [cited by examiner]
US 20120146091A1 · Tanabe et al. · 2012 [cited by applicant]
US 20180240867A1 · Nitta et al. · 2018 [cited by applicant]
U.S. Appl. No. 18/172,498, filed Feb. 22, 2023, Gouda et al. [cited by applicant]
Cited By (1)
US 12,684,809