Reducing precharge current surge in digital compute in memory
A compute-in-memory (CIM) device includes a memory cell and calculation circuitry configured to perform a calculation based on an input value and a value stored in the memory cell, and to provide a signal at an output node based on the calculation. The CIM device also includes write circuitry configured to perform a write operation on the memory cell and precharge circuitry configured to precharge the output node in response to the write circuitry performing the write operation.
1. A compute-in-memory (CIM) device, comprising:
a memory cell;
calculation circuitry configured to perform a calculation based on an input value and a value stored in the memory cell, and to provide a signal at an output node based on the calculation;
write circuitry configured to perform a write operation on the memory cell;
precharge circuitry configured to precharge the output node in response to the write circuitry performing the write operation; and
logic circuitry configured to detect that the write operation is being performed on the memory cell, and to control the precharge circuitry to precharge the output node in response to detecting that the write operation is being performed on the memory cell.
2. The CIM device of claim 1 , wherein the calculation comprises multiplication.
3. The CIM device of claim 1 , wherein the precharge circuitry comprises a transistor configured to precharge the output node by coupling the output node to a power rail.
4. The CIM device of claim 3 , wherein the transistor comprises a PMOS transistor.
5. The CIM device of claim 1 , wherein the precharge circuitry is configured to precharge the output node during the write operation.
6. The CIM device of claim 1 , wherein the value stored in the memory cell comprises a filter weight.
7. The CIM device of claim 1 , wherein the write circuitry is configured to perform write operations for a row of memory cells, and the precharge circuitry is configured to precharge output nodes of calculation circuitry configured to perform operations using values stored in the row of memory cells, wherein the precharge circuitry is configured to precharge the output nodes in response to the write operations.
8. The CIM device of claim 1 , wherein the precharge circuitry is configured to precharge the output node prior to the calculation being initiated.
9. The CIM device of claim 1 , wherein the memory cell includes a static random access memory (SRAM) cell and/or a ternary content addressable memory (TCAM) cell.
10. A compute-in-memory (CIM) method, comprising:
performing a write operation on a memory cell;
precharging an output node in response to the performing of the write operation;
performing a calculation based on an input value and a value stored in the memory cell and providing a signal at the output node based on the calculation; and
detecting that the write operation is being performed on the memory cell; and precharging the output node in response to detecting that the write operation is being performed on the memory cell.
11. The CIM method of claim 10 , wherein the calculation comprises multiplication.
12. The CIM method of claim 10 , wherein the precharging is performed through coupling the output node to a power rail using a transistor.
13. The CIM method of claim 12 , wherein the transistor comprises a PMOS transistor.
14. The CIM method of claim 10 , wherein the precharging is performed during the write operation.
15. The CIM method of claim 10 , wherein the value stored in the memory cell comprises a filter weight.
16. The CIM method of claim 10 , further comprising: performing write operations for a row of memory cells; and precharging, in response to the write operations, output nodes of calculation circuitry configured to perform operations using values stored in the row of memory cells.
17. The CIM method of claim 10 , wherein the precharging of the output node is performed prior to the calculation being initiated.
18. The CIM method of claim 10 , wherein the memory cell includes a static random access memory (SRAM) cell and/or a ternary content addressable memory (TCAM) cell.