Data processing apparatus, method and virtual machine
A data processing apparatus comprises processing circuitry to execute processing instructions, the processing circuitry comprising: a set of physical registers; instruction decoder circuitry to decode processing instructions; detector circuitry to detect groups of instructions which comply with a conflict condition, in which a group of instructions complies with the conflict condition at least when a given storage element is written to by a maximum of one instruction of that group of instructions; instruction issue circuitry to issue decoded instructions for execution; and instruction execution circuitry to execute instructions decoded by the instruction decoder circuitry.
1. A data processing apparatus comprising:
processing circuitry configured to execute processing instructions having an instruction order to generate one or more rows and/or one or more columns of an n×m matrix using a storage array having an n×m array of storage elements to hold one or more values generated by the instruction execution, where n and m are respective integers greater than one, each processing instruction defining one or more architectural registers to store one or more source operands, the processing circuitry comprising:
a set of physical registers;
instruction decoder circuitry configured to decode processing instructions;
detector circuitry configured to detect a groups of instructions having a maximum of one instruction of that group of instructions that writes to a given storage element;
instruction issue circuitry configured to issue decoded instructions for execution; and
instruction execution circuitry configured to execute instructions decoded by the instruction decoder circuitry, the instruction execution circuitry being configured to execute a decoded instruction by reference to one or more source operands stored by the set of architectural registers and to hold one or more values generated by that decoded instruction, the instruction execution circuitry comprising:
the storage array; and
out of order circuitry configured to selectively provide out of order execution of the group of processing instructions detected by the detector circuitry.
2. The apparatus of claim 1 , in which the processing circuitry is configured to selectively execute:
(i) processing instructions to generate some or all of an individual row or an individual column of the n×m matrix; and
(ii) processing instructions to generate a matrix region comprising a rectangular array representing some or all of the n×m matrix.
3. The apparatus of claim 1 , in which the detector circuitry is configured to detect successive groups with respect to the instruction order.
4. The apparatus of claim 3 , in which the detector circuitry is configured to associate a group identifier with each detected group of instructions, the group identifiers forming an ordered sequence indicative of an order of the detected groups with respect to the instruction order.
5. The apparatus of claim 4 , in which the group identifiers form a cyclic ordered sequence, in which a group identifier is made available for allocation to a next group of instructions by the detector circuitry when all instructions associated with that group identifier have been executed.
6. The apparatus of claim 5 , in which the detector circuitry is configured to stall operation in response to a next group identifier not being available.
7. The apparatus of claim 4 , in which the instruction issue circuitry is configured to maintain an issue queue of instructions awaiting issue and to associate a respective group identifier with each instruction in the issue queue.
8. The apparatus of claim 7 , in which the instruction issue circuitry is configured to selectively issue a given instruction directly to the instruction execution circuitry when the given instruction is in a group of instructions currently being executed by the instruction execution circuitry.
9. The apparatus of claim 3 , in which, for respective groups of instructions earlier and later with respect to the instruction order, the instruction execution circuitry is configured to defer execution of any instruction in the group of instructions later with respect to the instruction order at least until all instructions in the group of instructions earlier with respect to the instruction order have been issued for execution.
10. The apparatus of claim 9 , in which the instruction execution circuitry is configured, in response to cancellation of an instruction in a given instruction group, to cancel any already-issued instructions in an instruction group later with respect to the instruction order than the given instruction group.
11. The apparatus of claim 1 , in which the detector circuitry is configured to detect that a group of instructions complies with the conflict condition at least when a given storage element is accessed by a maximum of one instruction of that group of instructions.
12. The apparatus of claim 1 , in which the detector circuitry is configured to maintain a conflict register of n elements and to activate an mth element of the conflict register in response to an instruction accessing an mth row or an mth column of the n×m array of storage elements.
13. The apparatus of claim 1 , in which the detector circuitry is configured to maintain a conflict register having elements corresponding to respective partial regions of the n×m array of storage elements and to activate an element of the conflict register in response to an instruction accessing the respective partial region of the n×m array of storage elements, in which a group of instructions complies with the conflict condition at least when a given element of the conflict register is activated by a maximum of one instruction of that group of instructions.
14. The apparatus of claim 1 , in which:
the processing instructions are matrix processing instructions; and
the storage array is an accumulation array comprising an n×m array of accumulation elements.
15. A data processing method comprising:
executing processing instructions having an instruction order to generate one or more rows and/or one or more columns of an n×m matrix using a storage array having an n×m array of storage elements to hold one or more values generated by the instruction execution, where n and m are respective integers greater than one, each processing instruction defining one or more architectural registers to store one or more source operands, the executing step comprising:
decoding processing instructions;
detecting a groups of instructions having a maximum of one instruction of that group of instructions that writes to a given storage element;
issuing decoded instructions for execution; and
executing decoded instructions by reference to one or more source operands stored by the set of architectural registers and holding, using the storage array, one or more values generated by the decoded instructions, comprising selectively providing out of order execution of a group of processing instructions detected by the detector circuitry.
16. A virtual machine comprising a data processor to execute a computer program comprising machine readable instructions, in which execution of the computer program causes the data processor to operate as a data processing apparatus comprising:
processing circuitry configured to execute processing instructions having an instruction order to generate one or more rows and/or one or more columns of an n×m matrix using a storage array having an n×m array of storage elements to hold one or more values generated by the instruction execution, where n and m are respective integers greater than one, each processing instruction defining one or more architectural registers to store one or more source operands, the processing circuitry comprising:
a set of physical registers;
instruction decoder circuitry configured to decode processing instructions;
detector circuitry configured to detect a groups of instructions having a maximum of one instruction of that group of instructions that writes to a given storage element;
instruction issue circuitry configured to issue decoded instructions for execution; and
instruction execution circuitry configured to execute instructions decoded by the instruction decoder circuitry, the instruction execution circuitry being configured to execute a decoded instruction by reference to one or more source operands stored by the set of architectural registers and to hold one or more values generated by that decoded instruction, the instruction execution circuitry comprising:
the storage array; and
out of order circuitry configured to selectively provide out of order execution of a group of processing instructions detected by the detector circuitry.