Surface modification layer for conductive feature formation
Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.
1. A semiconductor device comprising:
a dielectric layer over a conductive region over a semiconductor substrate;
an opening through the dielectric layer and exposing the conductive region;
a monolayer of material lining the opening adjacent to the dielectric layer, the monolayer of material comprising a phosphoric acid derivative material; and
conductive material within the opening.
2. The semiconductor device of claim 1 , wherein the conductive material is in physical contact with the monolayer of material without a barrier layer.
3. The semiconductor device of claim 1 , further comprising a first etch stop layer located between the dielectric layer and the conductive region.
4. The semiconductor device of claim 3 , wherein the monolayer of material does not line the opening adjacent to the first etch stop layer.
5. The semiconductor device of claim 4 , further comprising a second etch stop layer located between the first etch stop layer and the conductive region.
6. The semiconductor device of claim 1 , wherein a thickness of the dielectric layer is in a range from 20 nm to 100 nm.
7. The semiconductor device of claim 1 , wherein the monolayer of material has a density between 1×10 15 atoms/cm 2 and 1×10 22 atoms/cm 2 .
8. A semiconductor device comprising:
an opening through a dielectric layer and exposing an underlying conductive region; and
a monolayer comprising phosphoric acid derivative molecules lining a sidewall of the opening adjacent to the dielectric layer, the monolayer having a thickness no thicker than a length of one of the phosphoric acid derivative molecules.
9. The semiconductor device of claim 8 , further comprising a conductive material within the opening and in physical contact with the monolayer, the conductive material not comprising a barrier layer.
10. The semiconductor device of claim 8 , wherein the opening has a width of between 5 nm and 40 nm.
11. The semiconductor device of claim 8 , wherein the opening has a depth of between about 30 nm to about 100 nm.
12. The semiconductor device of claim 8 , wherein the opening has a positive taper profile.
13. The semiconductor device of claim 8 , wherein the monolayer is a self-aligned monolayer.
14. The semiconductor device of claim 8 , wherein the monolayer has a thickness of between 1 nm and 2 nm.
15. A semiconductor device comprising:
a first conductive feature disposed within a first dielectric layer over a substrate;
a second conductive feature disposed between sidewalls of a second dielectric layer, the second conductive feature being free from a barrier layer; and
a surface modification layer in physical contact with both the second conductive feature and the second dielectric layer, the surface modification layer comprising phosphorous and carbon.
16. The semiconductor device of claim 15 , wherein the surface modification layer has a density in a range from 1×10 15 atoms/cm 2 to about 1×10 22 atoms/cm 2 .
17. The semiconductor device of claim 15 , wherein the second conductive feature is part of a middle end of line structure.
18. The semiconductor device of claim 15 , further comprising:
a first etch stop layer located between the second dielectric layer and the first dielectric layer; and
a second etch stop layer located between the first etch stop layer and the first dielectric layer.
19. The semiconductor device of claim 18 , wherein the first etch stop layer and the second etch stop layer are in physical contact with the second conductive feature.
20. The semiconductor device of claim 15 , wherein the surface modification layer has a thickness of between 1 nm and 2 nm.