Circuit structure and method for reducing electronic noises
In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.
1 . A semiconductor structure, comprising:
an active region over a substrate, the active region having a source region, a drain region, and a middle region between the source and drain regions along a first direction, wherein a width of the middle region is greater than a width of the source and drain regions along a second direction perpendicular to the first direction;
an isolation region surrounding the active region; and
a gate stack over the middle region, wherein the gate stack comprises a rectangular shape and overlaps the active region such that only four corner portions of the gate stack extending beyond the middle region are directly above the isolation region.
2 . The semiconductor structure of claim 1 , wherein the width of the middle region is greater than a width of the gate stack along the second direction.
3 . The semiconductor structure of claim 1 , wherein the source and drain regions are doped with a first type dopant, and the middle region is doped with a second type dopant opposite from the first type dopant.
4 . The semiconductor structure of claim 1 , wherein the middle region includes a channel region and a doping feature, and the doping feature extends along a first edge of the channel region in the first direction.
5 . The semiconductor structure of claim 4 , wherein the channel region and the doping feature are doped with a same type dopant, and the doping feature has a higher doping concentration than the channel region.
6 . The semiconductor structure of claim 4 ,
wherein the doping feature separates an edge of the gate stack from the isolation region,
wherein the edge extends along the first direction between two of the four corner portions.
7 . The semiconductor structure of claim 4 , wherein the doping feature is a low density doped (LDD) feature, and the middle region further includes a high density doped (HDD) feature that separates the LDD feature from the isolation region.
8 . The semiconductor structure of claim 7 , wherein the HDD feature includes a same type of dopant as the LDD feature, and the HDD feature has a doping concentration at least 10 times as high as that of the LDD feature.
9 . The semiconductor structure of claim 7 , wherein the LDD feature is shallower than the HDD feature in a vertical direction.
10 . The semiconductor structure of claim 4 , further comprising a gate spacer on sidewalls of the gate stack and directly above the doping feature.
11 . A semiconductor structure, comprising:
an active region over a substrate, the active region having a source region, a drain region, and a channel region between the source and drain regions along a first direction;
an isolation region surrounding the active region;
a gate stack over the channel region;
a first doping feature separating a first edge of the gate stack from the isolation region along a second direction perpendicular to the first direction; and
a second doping feature separating a second edge of the gate stack from the isolation region along the second direction,
wherein the first and second doping features span between corner portions of the gate stack, and the corner portions of the gate stack are directly above the isolation region,
wherein the channel region, the first doping feature, and the second doping feature are doped with a same dopant, and the first and second doping features have a higher doping concentration of the dopant than that of the channel region.
12 . The semiconductor structure of claim 11 , further comprising first and second gate spacers on sidewalls of the gate stack, wherein the first and second gate spacers are directly above the first and second doping features, respectively.
13 . The semiconductor structure of claim 11 , wherein the first doping feature extends continuously from the first edge of the gate stack to the isolation region along the second direction, and the second doping feature extends continuously from the second edge of the gate stack to the isolation region along the second direction.
14 . The semiconductor structure of claim 11 , further comprising a third doping feature separating the first doping feature from the isolation region, wherein the third doping feature has a higher concentration of the dopant than that of the first doping feature.
15 . The semiconductor structure of claim 14 , further comprising a fourth doping feature separating the second doping feature from the isolation region, wherein the fourth doping feature has a higher concentration of the dopant than that of the second doping feature.
16 . The semiconductor structure of claim 14 , wherein along the second direction, the first doping feature extends continuously from the first edge of the gate stack to the third doping feature, the third doping feature extends continuously from the first doping feature to the isolation region, and the second doping feature extends continuously from the second edge of the gate stack to the isolation region along the second direction.
17 . A semiconductor structure, comprising:
an active region over a substrate, the active region having a source region, a drain region, and a channel region between the source and drain regions along a first direction;
an isolation region surrounding the active region;
a gate stack over the channel region;
a first doping feature separating a first edge of the gate stack from the isolation region along a second direction perpendicular to the first direction; and
a second doping feature separating a second edge of the gate stack from the isolation region along the second direction,
wherein the first and second doping features each includes a low density doped (LDD) feature, the LDD feature of the first doping feature extends to interface a first sidewall of the isolation region,
wherein the second doping feature further includes a high density doped (HDD) feature with a doping concentration higher than that of the LDD feature, the HDD feature extends to interface a second sidewall of the isolation region.
18 . The semiconductor structure of claim 17 , wherein corner portions of the gate stack are directly above the isolation region, and wherein the first and second edges of the gate stack are between edges of the corner portions of the gate stack.
19 . The semiconductor structure of claim 17 , further comprising first and second gate spacers on sidewalls of the gate stack, wherein the first and second gate spacers are directly above the first and second doping features, respectively.
20 . The semiconductor structure of claim 17 ,
wherein the source and drain regions are doped with a first type dopant,
wherein the channel region, the first doping feature, and the second doping feature are doped with a second type dopant opposite from the first type dopant,
wherein the LDD feature has a doping concentration at least twice as high as that of a channel region, and the HDD feature includes a doping concentration that is at least 10 times as high as that of the LDD feature.