Granted Patent B2

US 12,476,535 · App. 18/182,518 · Granted Nov 18, 2025

Inventors: Hyunchul Eum (Chandler, AZ); Minha Hwang (Seoul, KR); Dhruv Chopra (Gilbert, AZ)

Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

H02M1/4208H02M1/12

Abstract

Claims (64)

1 . A method of operating a power-factor-correction (PFC) converter, the method comprising:

selecting a valley of a voltage signal at a switch node of the PFC converter;

charging an inductance of the PFC converter, thereby creating a charge mode, wherein charging is started in the selected valley of the voltage at the switch node;

asserting, during the charge mode, an initial-reset signal by a reset circuit implementing voltage-mode control;

ending the charge mode a compensated time after assertion of the initial-reset signal, the compensated time inversely proportional to a magnitude of an input voltage of the PFC converter; and then

discharging the inductance of the PFC converter,

wherein ending the charge mode comprises:

sampling a signal indicative of the magnitude of the input voltage and creating a digital voltage value;

dividing a proportionality value by the digital voltage value, and thereby creating a reference value;

responsive to asserting of the initial-reset signal, incrementing a counter creating a count value; and

ending the charge mode when the count value reaches the reference value.

2 . The method of claim 1 wherein ending the charge mode comprises:

sensing a signal indicative of the magnitude of the input voltage; and

setting the compensated time based on the signal indicative of the magnitude of the input voltage.

3 . The method of claim 2 wherein sensing the signal indicative of the magnitude of the input voltage comprises sensing the input voltage by way of a voltage divider coupled to the input voltage.

4 . The method of claim 2 wherein sensing the signal indicative of the magnitude of the input voltage comprises averaging a signal indicative of the voltage at the switch node of the PFC converter.

5 . The method of claim 2 wherein sensing the signal indicative of the magnitude of the input voltage comprises sensing a voltage of an auxiliary winding of a transformer, and wherein a primary winding of the transformer forms the inductance of the PFC converter.

6 . The method of claim 1 wherein ending the charge mode comprises, responsive to assertion of the initial-reset signal:

charging a capacitor with a charging current having a magnitude proportional to the magnitude of the input voltage; and

ending the charge mode when a voltage on the capacitor meets or exceeds a voltage reference.

7 . A power-factor-correction (PFC) controller for a PFC converter, the PFC controller comprising:

a sense terminal, a drive terminal, and a feedback terminal;

a charge-mode start controller defining a start output, the charge-mode start controller configured to assert the start output in a predetermined valley of a voltage at a switch node of the PFC converter;

a voltage-mode controller defining a feedback input coupled to the feedback terminal, and an initial-reset output, the voltage-mode controller configured to assert the initial-reset output by implementing voltage-mode control;

a driver defining a drive output coupled to the drive terminal, a start input coupled to the start output, and a reset input, the driver configured to assert the drive terminal responsive to assertion of the start input, and to de-assert the drive terminal responsive to assertion of the reset input;

a reset-delay controller defining a sense input coupled to the sense terminal, an initial-reset input coupled to the initial-reset output, and a final-reset output coupled to the reset input of the driver, the reset-delay controller configured to:

sense a signal indicative of magnitude of an input voltage of the PFC converter by way of the sense terminal, and

assert the final-reset output a compensated time after assertion of the initial-reset input, the compensated time inversely proportional to the signal indicative of magnitude of the input voltage,

wherein when the reset-delay controller asserts the final-reset output, the reset-delay controller is configured to:

sample the signal indicative of magnitude of the input voltage and create a digital voltage value;

divide a proportionality value by the digital voltage value, and thereby create a reference value;

responsive to assertion of the initial-reset input, begin incrementing a counter creating a count value; and

assert the final-reset output when the count value reaches the reference value.

8 . The PFC controller of claim 7 wherein when the reset-delay controller senses the signal indicative of magnitude of the input voltage, the reset-delay controller is further configured to sense the input voltage directly from the sense terminal.

9 . The PFC controller of claim 7 wherein when the reset-delay controller senses the signal indicative of magnitude of the input voltage, the reset-delay controller is further configured to average a signal indicative of the voltage at the switch node of the PFC converter, the signal indicative of voltage at the switch node applied to the sense terminal.

10 . The PFC controller of claim 7 wherein when the reset-delay controller senses the signal indicative of magnitude of the input voltage, the reset-delay controller is configured to sense a voltage of an auxiliary winding of a transformer coupled to the sense terminal.

11 . The PFC controller of claim 7 wherein when the reset-delay controller asserts the final-reset output, the reset-delay controller is configured to, responsive to assertion of the initial-reset input:

charge a capacitor with a charging current having a magnitude proportional to the signal indicative of magnitude of the input voltage; and

assert the final-reset output when a voltage on the capacitor meets or exceeds a reference voltage.

12 . A power-factor-correction (PFC) converter comprising:

an inductor with a first lead coupled to a voltage input and a second lead defining a switch node;

a rectifier with a first lead coupled to the switch node, and a second lead defining a voltage output of the PFC converter;

an electrically-controlled switch with a first lead coupled to the switch node, a second lead coupled to a reference voltage, and a control input;

a PFC controller comprising:

a charge-mode start controller defining a sense input coupled to a signal indicative of a voltage at the switch node, and a start output, the charge-mode start controller configured to assert the start output in a predetermined valley of the voltage at the switch node;

a voltage-mode controller defining a feedback input coupled to the voltage output, and an initial-reset output, the voltage-mode controller configured to assert the initial-reset output by implementing voltage-mode control;

a driver defining a drive output coupled to the control input of the electrically-controlled switch, a start input coupled to the start output, and a reset input, the driver configured to assert the control input responsive to assertion of the start input, and to de-assert the control input responsive to assertion of the reset input; and

a reset-delay controller defining a sense input, an initial-reset input coupled to the initial-reset output, and a final-reset output coupled to the reset input of the driver, the reset-delay controller configured to:

sense a signal indicative of magnitude of an input voltage of the PFC converter, and

assert the final-reset output an adjusted time after assertion of the initial-reset input, the adjusted time inversely proportional to the signal indicative of magnitude of the input voltage,

wherein when the reset-delay controller asserts the final-reset output, the reset-delay controller is configured to:

sample the signal indicative of magnitude of the input voltage and create a digital voltage value;

divide a proportionality value by the digital voltage value, and thereby create a reference value;

responsive to assertion of the initial-reset input, begin incrementing a counter creating a count value; and

assert the final-reset output when the count value reaches the reference value.

13 . The PFC converter of claim 12 wherein when the reset-delay controller senses the signal indicative of magnitude of the input voltage, the reset-delay controller is further configured to sense the input voltage directly at a sense terminal coupled to the voltage input.

14 . The PFC converter of claim 12 wherein when the reset-delay controller senses the signal indicative of magnitude of the input voltage, the reset-delay controller is further configured to average a signal indicative of the voltage at the switch node of the PFC converter applied to a sense terminal.

15 . The PFC converter of claim 12 further comprising:

a transformer in which the inductor is a primary winding of the transformer, and the transformer defines an auxiliary winding;

wherein when the reset-delay controller senses the signal indicative of magnitude of the input voltage, the reset-delay controller is further configured to sense a voltage of the auxiliary winding.

16 . The PFC converter of claim 12 wherein when the reset-delay controller asserts the final-reset output, the reset-delay controller is configured to, responsive to assertion of the initial-reset input:

charge a capacitor with a charging current having a magnitude proportional to the signal indicative of magnitude of the input voltage; and

assert the final-reset output when a voltage on the capacitor meets or exceeds a voltage reference.

17 . The PFC converter of claim 12 wherein a total harmonic distortion of an input current of the PFC converter is 5% or less.

Assignments (3)

Continuity (1)

References Cited (10)