MIPI C-PHY and D-PHY interface with shared driver, equalization, and data path circuitry
Imaging circuitry may include half-driver sub-circuits configured to support Mobile Industry Processor Interface (MIPI) D-PHY mode and C-PHY mode. Groups of two half-driver sub-circuits can be coupled together in the D-PHY mode, whereas groups of three half-driver sub-circuits can be coupled together in the C-PHY mode. Each half-driver sub-circuit can include one or more pull-up paths and one or more pull-down paths. Each half-driver sub-circuit can include multiple slices, a first portion of which can be operated to pull in a first direction and a second portion of which can be operated to pull in a second direction opposing the first direction to achieve the desired amount of equalization. The half-driver sub-circuits can be employed as the final driver stage of a shared data path architecture supporting both D-PHY and C-PHY modes. The shared data path can include serializers, pre-driver logic, and/or equalization enable blocks.
1. Circuitry comprising:
a plurality of half-driver sub-circuits operable in
(1) a first mode in which the half-driver sub-circuits are coupled together in groups of two and
(2) a second mode in which the half-driver sub-circuits are coupled together in groups of three, wherein each half-driver sub-circuit in the plurality of half-driver sub-circuit comprises:
a pull-up path having one or more pull-up transistors, and
a pull-down path having one or more pull-down transistors.
2. The circuitry of claim 1 , wherein the first mode comprises a Mobile Industry Processor Interface (MIPI) D-PHY mode, and wherein the second mode comprises a Mobile Industry Processor Interface (MIPI) C-PHY mode.
3. The circuitry of claim 2 , wherein the pull-up path includes at least first and second pull-up transistors and wherein the pull-down path includes at least first and second pull-down transistors.
4. The circuitry of claim 3 , wherein the first and second pull-up transistors comprise first and second n-type transistors and wherein the first and second pull-down transistors comprise third and fourth n-type transistors.
5. The circuitry of claim 3 , wherein the pull-up path further comprises:
a first resistor coupled at a drain terminal of the first pull-up transistor;
a second resistor coupled at a source terminal of the first pull-up transistor;
a third resistor coupled at a drain terminal of the second pull-up transistor; and
a fourth resistor coupled at a source terminal of the second pull-up transistor.
6. The circuitry of claim 3 , wherein the pull-up path further comprises:
a first resistor coupled at a drain terminal of the first pull-down transistor;
a second resistor coupled at a source terminal of the first pull-down transistor;
a third resistor coupled at a drain terminal of the second pull-down transistor; and
a fourth resistor coupled at a source terminal of the second pull-down transistor.
7. The circuitry of claim 6 , wherein the first, second, third, and fourth resistors have the same resistance value.
8. The circuitry of claim 3 , wherein:
during a D-PHY low state and a C-PHY low state, the first and second pull-down transistors are turned on while the first and second pull-up transistors are turned off;
during a D-PHY high state and a C-PHY high state, the first and second pull-down transistors are turned off while the first and second pull-up transistors are turned on;
during a C-PHY mid state, the first pull-down transistor and the first pull-up transistor are turned off while the second pull-down transistor and the second pull-up transistors are turned on; and
during a C-PHY float state, the first and second pull-down transistors and the first and second pull-up transistors are turned off.
9. The circuitry of claim 2 , wherein each half-driver sub-circuit in the plurality of half-driver sub-circuits includes m number of slices and wherein to perform equalization during the D-PHY mode, (m−j) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling in a first direction while j slices in each half-driver in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling in a second direction opposite to the first direction.
10. The circuitry of claim 2 , wherein each half-driver sub-circuit in the plurality of half-driver sub-circuits includes m number of slices and wherein to perform a high state equalization during the C-PHY mode, (m−n) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling up while n slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling down.
11. The circuitry of claim 2 , wherein each half-driver sub-circuit in the plurality of half-driver sub-circuits includes m number of slices and wherein to perform a low state equalization during the C-PHY mode, (m−n) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling down while n slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling up.
12. The circuitry of claim 2 , wherein each half-driver sub-circuit in the plurality of half-driver sub-circuits includes m number of slices and wherein to perform a first mid state equalization during the C-PHY mode, (m/2) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling down while (m/2) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling up.
13. The circuitry of claim 2 , wherein each half-driver sub-circuit in the plurality of half-driver sub-circuits includes m number of slices and wherein to perform a second mid state equalization during the C-PHY mode, (m/2+n) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling up while (m/2−n) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling down.
14. The circuitry of claim 2 , wherein each half-driver sub-circuit in the plurality of half-driver sub-circuits includes m number of slices and wherein to perform a third mid state equalization during the C-PHY mode, (m/2+n) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling down while (m/2−n) slices in each half-driver sub-circuit in the plurality of half-driver sub-circuits are pulling up.
15. Circuitry comprising:
inputs configured to receive parallel data bits;
a plurality of serializers;
a plurality of half-driver sub-circuits operable in (1) a first mode in which the half-driver sub-circuits are coupled together in groups of two and (2) a second mode in which the half-driver sub-circuits are coupled together in groups of three;
first pre-driver logic coupled between the inputs and the plurality of serializers; and
second pre-driver logic coupled between the plurality of serializers and the plurality of half-driver sub-circuits.
16. The circuitry of claim 15 , wherein the first mode comprises a Mobile Industry Processor Interface (MIPI) D-PHY mode, wherein the second mode comprises a Mobile Industry Processor Interface (MIPI) C-PHY mode, wherein the inputs are configured to receive groups of 16-bit parallel data in the D-PHY mode and are configured to receive groups of 21-bit parallel data in the C-PHY mode, wherein the plurality of serializers comprises a plurality of 8-bit serializers, wherein each of the 8-bit serializers are fully in use in the D-PHY mode, and wherein each of the 8-bit serializers has an unused portion in the C-PHY mode.
17. The circuitry of claim 16 , wherein the first pre-driver logic is configured to operate as a bypass block in the D-PHY mode and uses combinational logic within the first pre-driver logic to convert the parallel data bits to C-PHY pre-driver inputs in the C-PHY mode.
18. The circuitry of claim 16 , wherein the second pre-driver logic is configured to operate as a bypass block in the C-PHY mode and uses combinational logic within the second pre-driver logic to convert serialized data bits output from the plurality of serializers to complementary D-PHY pre-driver inputs in the D-PHY mode, and wherein the second pre-driver logic comprises a plurality of multiplexers configured to selectively bypass the combinational logic in the C-PHY mode.
19. The circuitry of claim 16 , further comprising:
equalization enable circuitry coupled between the second pre-driver logic and the plurality of half-driver sub-circuits, wherein the equalization enable circuitry is configured to operate a first portion of each half-driver sub-circuit to pull in a first direction and to operate a second portion of each half-driver sub-circuit to pull in a second direction opposing the first direction.
20. The circuitry of claim 15 , wherein each half-driver sub-circuit in the plurality of half-driver sub-circuits comprises:
a first pull-up transistor;
a second pull-up transistor;
a first pull-down transistor;
a second pull-down transistor;
first and second resistors coupled at drain and source terminals of the first pull-up transistor;
second and fourth resistors coupled at drain and source terminals of the second pull-up transistor;
fifth and sixth resistors coupled at drain and source terminals of the first pull-down transistor; and
seventh and eighth resistors coupled at drain and source terminals of the second pull-down transistor.