IP Library › Granted Patent US 12,550,790
Granted Patent B2
US 12,550,790 · App. 18/184,029 · Granted Feb 10, 2026

Stacked integrated circuit (IC) package

Inventors: Hun Seong Choi (Suwon-si, KR); Wooseok Chang (Suwon-si, KR); Junyeon Lee (Suwon-si, KR); Minkyu Kim (Suwon-si, KR); Byungwoo Bang (Suwon-si, KR); Jiye Choi (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L25/0657H01L23/50H01L25/18H10B80/00H01L2225/06544H01L2225/06589
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Quick Facts
Patent No.
US 12,550,790
App. No.
18/184,029
Granted
Feb 10, 2026
Kind
B2
Abstract

A stacked IC package includes a first die including a first power transmission region, an adapter die stacked on the first die, a second die stacked on the adapter die and including a second power transmission region, and a first power transmission path electrically connected between the second power transmission region and the first power transmission region through the adapter die. The first power transmission path includes a first power transmission part penetrating a portion of the adapter die in a vertical direction from the first power transmission region, a second power transmission part including a connected part in a horizontal direction from the first power transmission part in the adapter die, and a third power transmission part connected to the second power transmission region in the vertical direction from the second power transmission part. A voltage conversion circuit is arranged on the first power transmission path.

Claims (69)

1 . A stacked integrated circuit (IC) package comprising:

a first die comprising a first power transmission region;

a first adapter die stacked on the first die;

a second die stacked on the first adapter die and comprising a second power transmission region; and

a first power transmission path electrically connected between the second power transmission region and the first power transmission region through the first adapter die,

wherein the first power transmission path comprises:

a first power transmission part penetrating at least a portion of the first adapter die in a vertical direction from the first power transmission region;

a second power transmission part comprising a connected part in a horizontal direction from the first power transmission part in the first adapter die; and

a third power transmission part connected to the second power transmission region in the vertical direction from the second power transmission part, and

a voltage conversion circuit is arranged on the first power transmission path.

2 . The stacked IC package of claim 1 , wherein at least a portion of the first power transmission region does not overlap the second power transmission region in the vertical direction.

3 . The stacked IC package of claim 1 , wherein the voltage conversion circuit is arranged on the second power transmission part.

4 . The stacked IC package of claim 1 , wherein the second power transmission part is formed of a mesh type.

5 . The stacked IC package of claim 1 , wherein the first adapter die comprises silicone or a metal material and is configured to distribute heat generated in the first die or the second die.

6 . The stacked IC package of claim 1 , wherein the first die comprises a first signal transmission region,

the second die comprises a second signal transmission region, and

the stacked IC package comprises a first signal transmission path electrically connected between the second signal transmission region and the first signal transmission region through the first adapter die.

7 . The stacked IC package of claim 6 , wherein the first signal transmission path comprises:

a first signal transmission part penetrating at least a portion of the first adapter die in the vertical direction from the first signal transmission region;

a second signal transmission part comprising a connected part in the horizontal direction from the first signal transmission part in the first adapter die; and

a third signal transmission part connected to the second signal transmission region in the vertical direction from the second signal transmission part.

8 . The stacked IC package of claim 7 , wherein at least a portion of the first signal transmission region does not overlap the second signal transmission region in the vertical direction.

9 . The stacked IC package of claim 6 , further comprising a level shift circuit arranged on the first signal transmission path.

10 . The stacked IC package of claim 1 , further comprising a static read-only memory (SRAM) and at least one of a power management circuit for the first die and a power management circuit for the second die arranged in the first adapter die.

11 . The stacked IC package of claim 1 , further comprising:

a third die stacked on the second die and comprising a third power transmission region; and

a second power transmission path electrically connected between the third power transmission region and the first power transmission region through the first adapter die and the second die,

wherein the second power transmission path comprises:

a fourth power transmission part penetrating at least a portion of the first adapter die in the vertical direction from the first power transmission region;

a fifth power transmission part comprising a connected part in the horizontal direction from the fourth power transmission part in the first adapter die; and

a sixth power transmission part connected to the third power transmission region in the vertical direction from the fifth power transmission part by penetrating the second die, and

a second voltage conversion circuit is arranged on the fifth power transmission part.

12 . The stacked IC package of claim 1 , further comprising:

a second adapter die stacked on the second die;

a third die stacked on the second adapter die and comprising a third power transmission region; and

a second power transmission path electrically connected between the third power transmission region and the first power transmission region through the first adapter die, the second die, and the second adapter die,

wherein the second power transmission path comprises:

a fourth power transmission part penetrating at least a portion of the second adapter die in the vertical direction from the first power transmission region by penetrating the first adapter die and the second die;

a fifth power transmission part comprising a connected part in the horizontal direction from the fourth power transmission part in the second adapter die; and

a sixth power transmission part connected to the third power transmission region in the vertical direction from the fifth power transmission part, and

a second voltage conversion circuit is arranged on the fifth power transmission part.

13 . A stacked integrated circuit (IC) package comprising:

a logic die comprising a first power transmission region;

an adapter die stacked on the logic die;

a memory die stacked on the adapter die and comprising a second power transmission region; and

a power transmission path electrically connected between the second power transmission region and the first power transmission region through the adapter die,

wherein the power transmission path comprises:

a first power transmission part penetrating at least a portion of the adapter die in a vertical direction from the power transmission region;

a second power transmission part comprising a connected part in a horizontal direction from the first power transmission part in the adapter die; and

a third power transmission part connected to the second power transmission region in the vertical direction from the second power transmission part,

wherein a voltage conversion circuit is arranged in the second power transmission part, and

at least a portion of the first power transmission region does not overlap the second power transmission region in the vertical direction.

14 . The stacked IC package of claim 13 , wherein the second power transmission part is formed of a mesh type.

15 . The stacked IC package of claim 13 , further comprising a power management circuit for the memory die arranged in the adapter die.

16 . The stacked IC package of claim 13 , wherein the logic die comprises a first signal transmission region,

the memory die comprises a second signal transmission region, and

the stacked IC package comprises:

a first signal transmission path electrically connected between the second signal transmission region and the first signal transmission region through the adapter die.

17 . A stacked integrated circuit (IC) package comprising:

a first die;

an adapter die disposed on the first die along a first direction;

a second die disposed on the adapter die along the first direction such that the adapter die is at least partially disposed between the first die and the second die;

a first power transmission part extending along the first direction from a first end disposed at the first die to a second end disposed at the adapter die;

a second power transmission part extending along the first direction from a first end disposed at the second die to a second end disposed at the adapter die;

a third power transmission part extending in the first adapter die along a direction traverse to the first direction from the second end of the first power transmission part to the second end of the second power transmission part; and

a voltage conversion circuit arranged on one of the first power transmission part, the second power transmission part, and the third power transmission part.

18 . The stacked IC package of claim 17 , wherein the voltage conversion circuit is arranged on the third power transmission part.

19 . The stacked IC package of claim 17 , wherein the first die is a logic die and the second die is a memory die.

20 . The stacked IC package of claim 17 , wherein the first end of the first power transmission part is disposed in a first power transmission region of the first die, and the first end of the second power transmission part is disposed in a second power transmission region of the second die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2023
From: CHOI, HUN SEONG; CHANG, WOOSEOK; LEE, JUNYEON; KIM, MINKYU; BANG, BYUNGWOO; CHOI, JIYE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 062985/0775 →
Priority Claims (1)
KR 10-2022-0112253 · Sep 5, 2022 · national
Continuity (1)
Related Publication 20240079378A1 · Mar 7, 2024
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