Manufacturing method of a semiconductor device having high-voltage isolation capacitor

1 . A method for manufacturing a semiconductor device, the method comprising:

providing a high-voltage isolation capacitor region on a substrate;

forming a bottom electrode in the high-voltage isolation capacitor region;

forming an inter-metal dielectric layer on the bottom electrode;

forming a low bandgap dielectric layer on the inter-metal dielectric layer;

forming a first hard mask layer on the low bandgap dielectric layer;

patterning the first hard mask layer and the low bandgap dielectric layer to form a patterned first hard mask layer and a patterned low bandgap dielectric layer;

depositing a thick metal film on the patterned first hard mask layer and the patterned low bandgap dielectric layer; and

patterning the thick metal film to form a top electrode in the high-voltage isolation capacitor region,

wherein the top electrode overlaps the patterned first hard mask layer and the patterned low bandgap dielectric layer, and

wherein the patterned low bandgap dielectric layer comprises:

a first portion overlapping the top electrode and having a first thickness; and

a second portion not overlapping the top electrode and having a second thickness smaller than the first thickness.

2 . The method of claim 1 , further comprising:

forming a second hard mask layer on the thick metal film; and

patterning the second hard mask layer to form a patterned second hard mask layer on the top electrode.

3 . The method of claim 1 , further comprising:

forming a passivation layer on the patterned low bandgap dielectric layer and the top electrode, such that the passivation layer is in direct contact with the patterned low bandgap dielectric layer and the top electrode.

4 . The method of claim 1 , wherein the forming of the low bandgap dielectric layer on the inter-metal dielectric layer comprises:

forming a first sub-low bandgap dielectric layer having a first thickness on the inter-metal dielectric layer; and

forming a second sub-low bandgap dielectric layer having a second thickness greater than the first thickness on the first sub-low bandgap dielectric layer.

5 . The method of claim 1 , wherein the low bandgap dielectric layer comprises:

a first sub-low bandgap dielectric layer on the inter-metal dielectric layer; and

a second sub-low bandgap dielectric layer on the first sub-low bandgap dielectric layer.

6 . The method of claim 1 , further comprising:

providing a mixed-signal integrated circuit region adjacent to the high-voltage isolation capacitor region on the substrate, the providing of the mixed-signal integrated circuit region comprising:

forming an inter-metal line and a top via in the mixed-signal integrated circuit region; and

forming a top metal line connected to the top via,

wherein the low bandgap dielectric layer is not disposed below the top metal line.

7 . A method for manufacturing a semiconductor device, the method comprising:

providing a high-voltage isolation capacitor region on a substrate;

forming a bottom electrode in the high-voltage isolation capacitor region;

forming an inter-metal dielectric layer on the bottom electrode;

forming a low bandgap dielectric layer on the inter-metal dielectric layer in the high-voltage isolation capacitor region but not in a mixed-signal integrated circuit region;

forming a first hard mask layer on the low bandgap dielectric layer; and

forming a top electrode overlapping the bottom electrode,

wherein the top electrode overlaps the first hard mask layer and the low bandgap dielectric layer,

wherein the low bandgap dielectric layer comprises a first sub-low bandgap dielectric layer having a first thickness, and a second sub-low bandgap dielectric layer having a second thickness greater than the first thickness, and

wherein the second sub-low bandgap dielectric layer comprises a first portion overlapping the top electrode, and a second portion not overlapping the top electrode and having a thickness smaller than a thickness of the first portion.

8 . The method of claim 7 , further comprising:

forming a second hard mask layer on the top electrode; and

forming a passivation layer on the second hard mask layer,

wherein the passivation layer is in direct contact with the low bandgap dielectric layer and the top electrode.

9 . The method of claim 7 , further comprising:

providing the mixed-signal integrated circuit region adjacent to the high-voltage isolation capacitor region on the substrate, the providing of the mixed-signal integrated circuit region comprising:

forming an inter-metal line and a top via in the mixed-signal integrated circuit region; and

forming a top metal line connected to the top via,

wherein the low bandgap dielectric layer is not disposed below the top metal line.

10 . The method of claim 7 , further comprising:

forming a spacer insulating layer on the first hard mask layer; and

performing an etch-back process on the spacer insulating layer to form spacers on sidewalls of the low bandgap dielectric layer.

11 . The method of claim 9 , wherein the top electrode has a bottom surface located higher than a bottom surface of the top metal line.

12 . The method of claim 7 , wherein the low bandgap insulating layer has a bandgap lower than a bandgap of the inter-metal dielectric layer, and

wherein the first hard mask layer comprises a metal nitride layer.

13 . A method for manufacturing a semiconductor device, the method comprising:

providing a mixed-signal integrated circuit region and a high-voltage isolation capacitor region, respectively, on a substrate;

forming a bottom electrode in the high-voltage isolation capacitor region;

forming an inter-metal dielectric layer on the bottom electrode;

forming an inter-metal line and a top via in the mixed-signal integrated circuit region;

forming a low bandgap dielectric layer on the inter-metal dielectric layer;

forming a first hard mask layer on the low bandgap dielectric layer;

patterning the first hard mask layer and the low bandgap dielectric layer to form a patterned first hard mask layer and a patterned low bandgap dielectric layer;

depositing a thick metal film on the top via, the patterned first hard mask layer, and the patterned low bandgap dielectric layer;

patterning the thick metal film to form a top electrode in the high-voltage isolation capacitor region and a top metal line connected to the top via in the mixed-signal integrated circuit region; and

forming a passivation layer on the top metal line, the patterned low bandgap dielectric layer, and the top electrode,

wherein the top electrode overlaps the patterned first hard mask layer and the patterned low bandgap dielectric layer, and

wherein the low bandgap dielectric layer is not disposed below the top metal line.

14 . The method of claim 13 , wherein the patterned low bandgap dielectric layer comprises:

a first portion overlapping the top electrode and having a first thickness; and

a second portion not overlapping the top electrode and having a second thickness smaller than the first thickness.

15 . The method of claim 13 , wherein the low bandgap dielectric layer comprises:

a first sub-low bandgap dielectric layer having a first thickness; and

a second sub-low bandgap dielectric layer having a second thickness greater than the first thickness.

16 . The method of claim 15 , wherein the second sub-low bandgap dielectric layer comprises:

a first portion overlapping the top electrode; and

a second portion not overlapping the top electrode and having a thickness smaller than a thickness of the first portion.