Input-adaptive analog-to-digital conversion
Aspects of the present disclosure provide input-adaptive analog-to-digital conversion in which the number of conversion cycles used to convert an input signal into a digital signal is adapted based on the level (i.e., amplitude) of the input voltage. In certain aspects, the input voltage is compared with one or more threshold voltages, and the number of conversion cycles is determined based on the comparison. In certain aspects, a most significant bit (MSB) capacitor in a capacitive digital-to-analog (DAC) is split into two or more capacitors to provide the one or more threshold voltages.
1. An analog-to-digital converter (ADC), comprising:
a comparator having a first input, a second input, and an output;
a successive approximation register (SAR) coupled to the output of the comparator; and
a capacitive digital-to-analog converter (DAC) having an input and an output, wherein the input of the capacitor DAC is configured to receive an input voltage, and the output of the capacitive DAC is coupled to the first input of the comparator, the capacitive DAC comprising:
binary-weighted capacitors, wherein the binary-weighted capacitors include a most significant bit (MSB) capacitor and lower-order capacitors, the MSB capacitor has a largest capacitance among the binary-weighted capacitors, the MSB capacitor comprises a first capacitor and a second capacitor, a first terminal of the first capacitor is coupled to the output of the capacitive DAC, a first terminal of the second capacitor is coupled to the output of the capacitive DAC, and a first terminal of each of the lower-order capacitors is coupled to the output of the capacitive DAC; and
a switching circuit coupled to the SAR, to a second terminal of the first capacitor, to a second terminal of the second capacitor, and to a second terminal of each of the lower-order capacitors;
wherein the SAR is configured to:
cause the switching circuit to couple the second terminal of the second capacitor to a first voltage, couple the second terminal of the first capacitor to a second voltage, and couple the second terminal of each of the lower-order capacitors to the first voltage; and
determine whether the input voltage is greater than or less than a threshold voltage based on a compare signal from the comparator; and
wherein, if the input voltage is less than the threshold voltage, the SAR is further configured to:
cause the switching circuit to couple the second terminal of the first capacitor and the second terminal of the second capacitor to the second voltage, and couple the second terminal of each of the lower-order capacitors to the first voltage; and
resolve a most significant bit of a digital signal based on the compare signal from the comparator.
2. The ADC of claim 1 , wherein the switching circuit comprises:
a first switch coupled to the second terminal of the first capacitor, wherein the first switch is configured to selectively couple the second terminal of the first capacitor to the input of the capacitive DAC, to a first voltage, or to a second voltage based on a first control signal from the SAR; and
a second switch coupled to the second terminal of the second capacitor, wherein the second switch is configured to selectively couple the second terminal of the second capacitor to the input of the capacitive DAC, to the first voltage, or to the second voltage based on a second control signal from the SAR.
3. The ADC of claim 2 , wherein the second input of the comparator is coupled to a third voltage.
4. The ADC of claim 3 , wherein the third voltage is at a ground potential.
5. The ADC of claim 2 , wherein the first voltage is at a ground potential.
6. The ADC of claim 1 , wherein a sum of a capacitance of the first capacitor and a capacitance of the second capacitor is approximately equal to a sum of capacitances of the lower-order capacitors.
7. The ADC of claim 1 , wherein the SAR is configured to:
determine the input voltage is greater than the threshold voltage if the compare signal has a first logic value; and
determine the input voltage is less than the threshold voltage if the compare signal has a second logic value.
8. The ADC of claim 1 , wherein the SAR is configured:
resolve the most significant bit of the digital signal to a bit value of one if the compare signal has a first logic value; and
resolve the most significant bit of the digital signal to a bit value of zero if the compare signal has a second logic value.
9. The ADC of claim 1 , wherein, if the input voltage is less than the threshold voltage, the SAR is configured to:
for each one of last m bits of the digital signal,
couple the second terminal of a respective one of the lower-order capacitors to the second voltage; and
resolve the one of the last m bits of the digital signal based on the compare signal from the comparator;
wherein m is less than a total number of bits of the digital signal.
10. The ADC of claim 9 , wherein the SAR is configured to output the resolved last m bits and output a bit value of zero for each bit of the digital signal having a higher order than the last m bits of the digital signal.
11. The ADC of claim 9 , wherein the SAR is configured to:
for each one of the last m bits of the digital signal,
resolve the one of the m bits to a bit value of one if the compare signal has a first logic value; and
resolve the one of the last m bits to a bit value of zero if the compare signal has a second logic value.
12. The ADC of claim 1 , wherein the MSB capacitor further comprises a third capacitor, wherein a first terminal of the third capacitor is coupled to the output of the capacitive DAC, and a second terminal of the third capacitor is coupled to the switching circuit.
13. The ADC of claim 12 , wherein a sum of a capacitance of the first capacitor, a capacitance of the second capacitor, and a capacitance of the third capacitor is approximately equal to a sum of capacitances of the lower-order capacitors.
14. The ADC of claim 12 , wherein the SAR is configured to:
cause the switching circuit to couple the second terminal of the second capacitor to a first voltage, couple the second terminal of the third capacitor to the first voltage, couple the second terminal of the first capacitor to a second voltage, and couple the second terminal of each of the lower-order capacitors to the first voltage; and
determine whether the input voltage is greater than or less than a first threshold voltage based on a compare signal from the comparator.
15. The ADC of claim 14 , wherein the SAR is configured to:
determine the input voltage is greater than the first threshold voltage if the compare signal has a first logic value; and
determine the input voltage is less than the first threshold voltage if the compare signal has a second logic value.
16. The ADC of claim 14 , wherein, if the input voltage is less than the first threshold voltage, the SAR is configured to:
for each one of last m bits of a digital signal,
couple the second terminal of a respective one of the lower-order capacitors to the second voltage; and
resolve the one of the last m bits of the digital signal based on the compare signal from the comparator;
wherein m is less than a total number of bits of the digital signal.
17. The ADC of claim 16 , wherein, if the input voltage is greater than the first threshold voltage, the SAR is configured to:
cause the switching circuit to couple the second terminal of the first capacitor and the second terminal of the third capacitor to the second voltage, couple the second terminal of the second capacitor to the first voltage, and couple the second terminal of each of the lower-order capacitors to the first voltage; and
determine whether the input voltage is greater than or less than a second threshold voltage based on the compare signal from the comparator, wherein the second voltage is greater than the first threshold voltage.
18. The ADC of claim 17 , wherein, if the input voltage is greater than the second threshold voltage, the SAR is configured to:
cause the switching circuit to couple the second terminal of the first capacitor, the second terminal of the second capacitor, and the second terminal of the third capacitor to the second voltage, and couple the second terminal of each of the lower-order capacitors to the first voltage; and
resolve a most significant bit of a digital signal based on the compare signal from the comparator.
19. The ADC of claim 18 , wherein the SAR is configured:
resolve the most significant bit of the digital signal to a bit value of one if the compare signal has a first logic value; and
resolve the most significant bit of the digital signal to a bit value of zero if the compare signal has a second logic value.
20. The ADC of claim 18 , wherein, if the input voltage is less than the second threshold voltage, the SAR is configured to:
for each one of last k bits of the digital signal,
couple the second terminal of a respective one of the lower-order capacitors to the second voltage; and
resolve the one of the last k bits of the digital signal based on the compare signal from the comparator;
wherein k is less than a total number of bits of the digital signal.
21. The ADC of claim 1 , wherein, during a sampling phase, the SAR is configured to cause the switching circuit to couple the second terminal of the first capacitor, the second terminal of the second capacitor, and the second terminal of each of the lower-order capacitors to the input of the capacitive DAC.
22. The ADC of claim 21 , further comprising a switch coupled between the output of the capacitive DAC and a voltage, wherein the switch is closed during the sampling phase.
23. The ADC of claim 22 , wherein the voltage is at ground potential.
24. An analog-to-digital converter (ADC), comprising:
a comparator having a first input, a second input, and an output;
a successive approximation register (SAR) coupled to the output of the comparator; and
a first capacitive digital-to-analog converter (DAC) having an input and an output, wherein the input of the first capacitor DAC is configured to receive a first input voltage, and the output of the first capacitive DAC is coupled to the first input of the comparator, the first capacitive DAC comprising:
first binary-weighted capacitors, wherein the first binary-weighted capacitors include a first most significant bit (MSB) capacitor and first lower-order capacitors, the first MSB capacitor has a largest capacitance among the first binary-weighted capacitors, the first MSB capacitor comprises a first capacitor and a second capacitor, a first terminal of the first capacitor is coupled to the output of the first capacitive DAC, a first terminal of the second capacitor is coupled to the output of the first capacitive DAC, and a first terminal of each of the first lower-order capacitors is coupled to the output of the first capacitive DAC; and
a first switching circuit coupled to the SAR, to a second terminal of the first capacitor, to a second terminal of the second capacitor, and to a second terminal of each of the first lower-order capacitors; and
a second DAC having an input and an output, wherein the input of the second capacitor DAC is configured to receive a second input voltage, and the output of the second capacitive DAC is coupled to the second input of the comparator, the second capacitive DAC comprising:
second binary-weighted capacitors, wherein the second binary-weighted capacitors include a second MSB capacitor and second lower-order capacitors, the second MSB capacitor has a largest capacitance among the second binary-weighted capacitors, the second MSB capacitor comprises a third capacitor and a fourth capacitor, a first terminal of the third capacitor is coupled to the output of the second capacitive DAC, a first terminal of the fourth capacitor is coupled to the output of the second capacitive DAC, and a first terminal of each of the second lower-order capacitors is coupled to the output of the second capacitive DAC; and
a second switching circuit coupled to the SAR, to a second terminal of the third capacitor, to a second terminal of the fourth capacitor, and to a second terminal of each of the second lower-order capacitors;
wherein the SAR is configured to:
cause the first switching circuit to couple the second terminal of the second capacitor and the second terminal of each of the first lower-order capacitors to a first voltage, and couple the second terminal of the first capacitor to a second voltage;
cause the second switching circuit to couple the second terminal of the third capacitor, the second terminal of the fourth capacitor, and the second terminal of each of the second lower-order capacitors to the first voltage; and
determine whether a difference between the first input voltage and the second input voltage is greater than or less than a threshold voltage based on a compare signal from the comparator.
25. The ADC of claim 24 , wherein the first switching circuit comprises:
a first switch coupled to the second terminal of the first capacitor, wherein the first switch is configured to selectively couple the second terminal of the first capacitor to a first voltage or to a second voltage based on a first control signal from the SAR; and
a second switch coupled to the second terminal of the second capacitor, wherein the second switch is configured to selectively couple the second terminal of the second capacitor to the first voltage or to the second voltage based on a second control signal from the SAR.
26. The ADC of claim 25 , wherein the second switching circuit comprises:
a third switch coupled to the second terminal of the third capacitor, wherein the third switch is configured to selectively couple the second terminal of the third capacitor to the first voltage or to the second voltage based on a third control signal from the SAR; and
a fourth switch coupled to the second terminal of the fourth capacitor, wherein the fourth switch is configured to selectively couple the second terminal of the fourth capacitor to the first voltage or to the second voltage based on a fourth control signal from the SAR.
27. The ADC of claim 24 , wherein a sum of a capacitance of the first capacitor and a capacitance of the second capacitor is approximately equal to a sum of capacitances of the first lower-order capacitors.
28. The ADC of claim 27 , wherein a sum of a capacitance of the third capacitor and a capacitance of the fourth capacitor is approximately equal to a sum of capacitances of the second lower-order capacitors.
29. The ADC of claim 24 , wherein the SAR is configured to:
determine the difference between the first input voltage and the second input voltage is greater than the threshold voltage if the compare signal has a first logic value; and
determine the difference between the first input voltage and the second input voltage is less than the threshold voltage if the compare signal has a second logic value.
30. The ADC of claim 24 , wherein, if the difference between the first input voltage and the second input voltage is greater than the threshold voltage, the SAR is configured to:
cause the first switching circuit to couple the second terminal of the first capacitor and the second terminal of the second capacitor to the second voltage, and couple the second terminal of each of the first lower-order capacitors to the first voltage;
cause the second switching circuit to couple the second terminal of the third capacitor, the second terminal of the fourth capacitor, and the second terminal of each of the second lower-order capacitors to the first voltage; and
resolve a most significant bit of a digital signal based on the compare signal from the comparator.
31. The ADC of claim 30 , wherein the SAR is configured:
resolve the most significant bit of the digital signal to a bit value of one if the compare signal has a first logic value; and
resolve the most significant bit of the digital signal to a bit value of zero if the compare signal has a second logic value.
32. The ADC of claim 30 , wherein, if the difference between the first input voltage and the second input voltage is less than the threshold voltage, the SAR is configured to:
for each one of last m bits of the digital signal,
couple the second terminal of a respective one of the first lower-order capacitors to the second voltage if a previous resolved bit is one or couple the second terminal of a respective one of the second lower-order capacitors to the second voltage if the previous resolved bit is zero; and
resolve the one of the last m bits of the digital signal based on the compare signal from the comparator;
wherein m is less than a total number of bits of the digital signal.
33. The ADC of claim 32 , wherein the SAR is configured to output the resolved m bits and output a bit value of zero for each bit of the digital signal having a higher order than the m bits of the digital signal.
34. The ADC of claim 32 , wherein the SAR is configured to:
for each one of the last m bits of the digital signal,
resolve the one of the last m bits to a bit value of one if the compare signal has a first logic value; and
resolve the one of the last m bits to a bit value of zero if the compare signal has a second logic value.
35. The ADC of claim 24 , wherein the first MSB capacitor further comprises a fifth capacitor, wherein a first terminal of the fifth capacitor is coupled to the output of the first capacitive DAC, and a second terminal of the fifth capacitor is coupled to the first switching circuit.
36. The ADC of claim 35 , wherein a sum of a capacitance of the first capacitor, a capacitance of the second capacitor, and a capacitance of the fifth capacitor is approximately equal to a sum of capacitances of the first lower-order capacitors.
37. The ADC of claim 35 , wherein the second MSB capacitor further comprises a sixth capacitor, wherein a first terminal of the sixth capacitor is coupled to the output of the second capacitive DAC, and a second terminal of the sixth capacitor is coupled to the second switching circuit.
38. The ADC of claim 37 , wherein:
a sum of a capacitance of the first capacitor, a capacitance of the second capacitor, and a capacitance of the fifth capacitor is approximately equal to a sum of capacitances of the first lower-order capacitors; and
a sum of a capacitance of the third capacitor, a capacitance of the fourth capacitor, and a capacitance of the sixth capacitor is approximately equal to a sum of capacitances of the second lower-order capacitors.