Backside via with a low-k spacer

1. A method, comprising:

receiving a workpiece comprising:

a plurality of nanostructures disposed over a substrate, and

a source/drain feature in contact with sidewalls of the plurality of nanostructures and disposed over a semiconductor plug extending into the substrate,

wherein the workpiece comprises a bottom surface adjacent to the substrate and a top surface away from the substrate;

forming a hard mask over the bottom surface to cover the semiconductor plug, wherein the hark mask is wider than a bottom surface of the semiconductor plug such that a vertical projection area of the semiconductor plug falls within a vertical projection area of the hard mask;

etching the substrate from the bottom surface of the workpiece to form a dielectric opening using the hard mask as a mask, such that a portion of the substrate covered by the hard mask remains;

forming a backside dielectric layer in the dielectric opening;

replacing the semiconductor plug with a backside contact; and

selectively removing the remaining portion of the substrate to form a gap therein.

2. The method of claim 1 , wherein the forming of the hard mask comprises:

performing a first etching process to etch the semiconductor plug and the substrate from the bottom surface of the workpiece to form a recess; and

forming the hard mask in the recess,

wherein the first etching process etches the semiconductor plug at a rate greater than etching the substrate.

3. The method of claim 2 , wherein the first etching process comprises using a wet etching process to selectively etch the semiconductor plug.

4. The method of claim 1 , wherein the gap is horizontally surrounded by the backside dielectric layer and between the backside dielectric layer and the backside contact.

5. The method of claim 1 , wherein the replacing of the semiconductor plug with the backside contact comprises:

performing a second etching process to selectively remove the semiconductor plug without substantially damaging the remaining portion of the substrate to form a contact opening; and

forming the backside contact in the contact opening.

6. The method of claim 5 , further comprising:

before the forming of the backside contact in the contact opening, forming a dielectric barrier layer over sidewalls of the contact opening, such that the source/drain feature is exposed in the contact opening.

7. The method of claim 1 , wherein the etching of the substrate from the bottom surface of the workpiece and the selectively removing of the remaining portion of the substrate comprise dry etching processes implementing CF 4 , Cl 2 , NF 3 , or HBr.

8. The method of claim 1 , further comprising:

depositing an interlayer dielectric layer over the gap; and

forming a backside power rail in the interlayer dielectric layer.

9. A semiconductor device, comprising:

two stacks of channel members;

a source/drain feature extending between the two stacks of channel members along a direction;

a source/drain contact disposed under and electrically coupled to the source/drain feature;

two gate structures over and interleaved with the two stacks of channel members;

a low-k spacer horizontally surrounding the source/drain contact;

a dielectric layer horizontally surrounding the low-k spacer;

an insulation layer disposed under the source/drain contact; and

a backside power rail embedded in the insulation layer and electrically connected to the source/drain contact.

10. The semiconductor device of claim 9 , further comprising:

a liner disposed between the source/drain contact and the low-k spacer.

11. The semiconductor device of claim 9 , further comprising:

two spacers in the two stacks of channel members and between the source/drain feature and the two gate structures,

wherein the two spacers are each wider than the low-k spacer along the direction.

12. The semiconductor device of claim 11 , wherein a portion of bottom surfaces of the two spacers directly contacts the dielectric layer.

13. The semiconductor device of claim 11 , wherein a topmost surface of the low-k spacer is in direct contact with at least one of the two spacers.

14. The semiconductor device of claim 9 , wherein the low-k spacer comprises an air gap.

15. The semiconductor device of claim 9 , wherein a ratio of a width of the low-k spacer along the direction to a width of the source/drain contact along the direction is between about 0.1 and about 0.2.

16. A semiconductor device, comprising:

a channel region;

a source feature and a drain feature sandwiching the channel region along a direction;

a gate structure over the channel region;

a dielectric layer under the channel region and the drain feature;

a source contact disposed directly under the source feature; and

an air gap disposed between the dielectric layer and the source contact.

17. The semiconductor device of claim 16 , further comprising:

a liner disposed between the dielectric layer and the source contact along the direction.

18. The semiconductor device of claim 17 , wherein the air gap wraps around a sidewall of the liner.

19. The semiconductor device of claim 16 , further comprising:

a backside power rail disposed under and electrically connected to the source contact.

20. The semiconductor device of claim 16 , further comprising:

an inner spacer disposed in the channel region and exposed to the air gap,

wherein a width of the inner spacer along the direction is greater than a width of the air gap along the direction.