IP Library › Granted Patent US 12,387,792

Granted Patent B2

US 12,387,792 · App. 18/190,577 · Granted Aug 12, 2025

Memory device and operating method thereof

Inventor: Steve S. Chung (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MEMORY INC.

G11C16/102 G11C16/0433 G11C16/08

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Quick Facts

Patent No.: US 12,387,792
App. No.: 18/190,577
Granted: Aug 12, 2025
Kind: B2

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Abstract

A memory device includes a first storage transistor and a first select transistor. The first storage transistor is configured to store a first data bit. The first select transistor is configured to change the resistance of a gate of the first storage transistor, to write the first data bit into the first storage transistor, a first terminal of the first select transistor being coupled to the gate of the first storage transistor. A method of operating a memory device is also disclosed herein.

Claims (70)

1. A memory device, comprising:

a first storage transistor configured to store a first data bit; and

a first select transistor configured to change a resistance of a gate of the first storage transistor, to write the first data bit into the first storage transistor, a first terminal of the first select transistor being coupled to the gate of the first storage transistor,

wherein a first terminal of the first storage transistor is configured to output a bit line signal, and a second terminal of the first storage transistor is configured to connect to a select line signal different from the bit line signal.

2. The memory device of claim 1 , wherein the first select transistor is further configured to provide a first word line signal to the gate of the first storage transistor, and

when the first data bit is written into the first storage transistor, the first word line signal flows through the gate of the first storage transistor and the second terminal of the first storage transistor.

3. The memory device of claim 2 , wherein

when the first data bit is written into the first storage transistor and the first word line signal has a first current level, the gate of the first storage transistor is maintained at a first resistance, and

when the first data bit is written into the first storage transistor and the first word line signal has a second current level larger than the first current level, the gate of the first storage transistor is changed to a second resistance larger than the first resistance.

4. The memory device of claim 2 , wherein the first storage transistor is configured to generate a first current corresponding to the first data bit, and

the first current flows through the second terminal of the first storage transistor and the first terminal of the first storage transistor.

5. The memory device of claim 1 , further comprising:

a second storage transistor configured to store a second data bit, a first terminal of the second storage transistor being coupled to the first terminal of the first storage transistor,

wherein the first select transistor is further configured to change a resistance of a gate of the second storage transistor, to write the second data bit into the second storage transistor, the first terminal of the first select transistor being coupled to the gate of the second storage transistor.

6. The memory device of claim 5 , further comprising:

a third storage transistor configured to store a third data bit, a first terminal of the third storage transistor being coupled to the second terminal of the first storage transistor; and

a second select transistor configured to be turned on when the first select transistor is turned on, and configured to change a resistance of a gate of the third storage transistor, to write the third data bit into the third storage transistor, a first terminal of the second select transistor being coupled to the gate of the third storage transistor.

7. The memory device of claim 1 , wherein the first select transistor is further configured to provide a pulse signal to the gate of the first storage transistor.

8. A method of operating a memory device, comprising:

writing a first logic value or a second logic value into a first storage transistor, comprising:

providing a first word line signal to a gate of the first storage transistor by a first select transistor;

when the first word line signal has a first voltage level corresponding to the first logic value, changing the gate of the first storage transistor to a first resistance; and

when the first word line signal has a second voltage level corresponding to the second logic value, maintaining the gate of the first storage transistor at a second resistance,

9. The method of claim 8 , further comprising:

after writing the first logic value or the second logic value into the first storage transistor, writing the first logic value or the second logic value into a second storage transistor, comprising:

providing the first word line signal to a gate of the second storage transistor by the first select transistor;

when the first word line signal has the first voltage level, changing the gate of the second storage transistor to the first resistance; and

when the first word line signal has the second voltage level, maintaining the gate of the second storage transistor at the second resistance,

wherein a first terminal of the second storage transistor is coupled to the first terminal of the first storage transistor.

10. The method of claim 9 , further comprising:

during writing the first logic value or the second logic value into the first storage transistor, writing the first logic value or the second logic value into a third storage transistor, comprising:

providing a second word line signal to a gate of the third storage transistor by a second select transistor;

when the second word line signal has the first voltage level, changing the gate of the third storage transistor to the first resistance; and

when the second word line signal has the second voltage level, maintaining the gate of the third storage transistor at the second resistance,

wherein a first terminal of the third storage transistor is coupled to the second terminal of the first storage transistor.

11. The method of claim 8 , further comprising:

after writing the first logic value or the second logic value into the first storage transistor, reading the first logic value or the second logic value stored in the first storage transistor, comprising:

generating a first current by the first storage transistor,

wherein when the first storage transistor has the first logic value, the first current has a first current level, and

when the first storage transistor has the second logic value, the first current has a second current level different from the first current level.

12. The method of claim 11 , further comprising:

during reading the first logic value or the second logic value stored in the first storage transistor, reading the first logic value or the second logic value stored in a second storage transistor, comprising:

generating a second current by the second storage transistor,

wherein the second terminal of the first storage transistor is coupled to a first terminal of the second storage transistor,

the first current flows through the first terminal of the first storage transistor and the second terminal of the first storage transistor, and

the second current flows through the first terminal of the second storage transistor and a second terminal of the second storage transistor.

13. The method of claim 12 , further comprising:

after reading the first logic value or the second logic value stored in the first storage transistor, reading the first logic value or the second logic value stored in a third storage transistor, comprising:

generating a third current by the third storage transistor,

wherein the first terminal of the first storage transistor is coupled to a first terminal of the third storage transistor, and

a control terminal of the first storage transistor is coupled to a control terminal of the third storage transistor.

14. A memory device, comprising:

a first storage transistor configured to store a first data bit according to a first word line signal, a gate of the first storage transistor being configured to connect to the first word line signal; and

a first select transistor configured to change a voltage level of a first terminal of the first storage transistor, to write the first data bit into the first storage transistor, a first terminal of the first select transistor being coupled to the first terminal of the first storage transistor,

wherein a second terminal of the first storage transistor is configured to output a bit line signal, and the first terminal of the first storage transistor is configured to receive a select line signal different from the bit line signal.

15. The memory device of claim 14 , wherein when the first data bit is written into the first storage transistor, the first word line signal flows through the gate of the first storage transistor and the first terminal of the first storage transistor.

16. The memory device of claim 14 , wherein

17. The memory device of claim 14 , wherein the first storage transistor is configured to generate a first current corresponding to the first data bit, and

the first current flows through the second terminal of the first storage transistor and the first terminal of the first storage transistor.

18. The memory device of claim 14 , further comprising:

a second storage transistor configured to store a second data bit according to a second word line signal, a gate of the second storage transistor being configured to connect to the second word line signal, a first terminal of the second storage transistor being coupled to the first terminal of the first storage transistor,

wherein the first select transistor is further configured to change a voltage level of the first terminal of the second storage transistor, to write the second data bit into the second storage transistor.

19. The memory device of claim 18 , further comprising:

a third storage transistor configured to store a third data bit according to the first word line signal, a gate of the third storage transistor being configured to connect to the first word line signal; and

a second select transistor configured to change a voltage level of a first terminal of the third storage transistor, to write the third data bit into the third storage transistor, a first terminal of the second select transistor being coupled to the first terminal of the second storage transistor.

20. The memory device of claim 19 , wherein a second terminal of the third storage transistor is coupled to the second terminal of the first storage transistor, and

the first select transistor and the second select transistor are turned on in order.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2023

From: CHUNG, STEVE S.

To: TAIWAN SEMICONDUCTOR MEMORY INC.

Reel/Frame 063132/0274 →

Priority Claims (1)

TW 111114499 · Apr 15, 2022 · national

Continuity (1)

Related Publication 20230335197A1 · Oct 19, 2023

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