Semiconductor devices and data storage systems including the same
A semiconductor device includes a substrate, circuit devices on the substrate, lower interconnection lines electrically connected to the circuit devices, a peripheral region insulating layer covering the lower interconnection lines, a source structure on the peripheral region insulating layer, gate electrodes stacked and spaced apart from each other in a first direction on the source structure, channel structures penetrating through the gate electrodes and each including a channel layer, contact plugs penetrating through the gate electrodes and the source structure, extending in the first direction, and connected to a portion of the lower interconnection lines, and spacer layers between the contact plugs and the source structure and including a material different from a material of the insulating layer in the peripheral region, wherein each of the spacer layers has a first width on an upper surface and has a second width greater than the first width on a lower surface.
1 . A semiconductor device, comprising:
a first semiconductor structure including a substrate, circuit devices on the substrate, lower interconnection lines on the circuit devices, and a peripheral region insulating layer covering the lower interconnection lines; and
a second semiconductor structure on the first semiconductor structure, having first and second regions, and including,
a source structure,
gate electrodes stacked on the source structure and spaced apart from each other in a first direction perpendicular to an upper surface of the source structure,
channel structures penetrating the gate electrodes in the first region, the channel structures extending in the first direction, and each of the channel structures including a channel layer,
contact plugs extending in the first direction in the second region, the contact plugs penetrating through the gate electrodes and the source structure, and the contact plugs connected to a portion of the lower interconnection lines, and
spacer layers between the contact plugs and the source structure,
wherein the spacer layers include a material different from a material of the peripheral region insulating layer,
wherein each of the contact plugs includes a first portion on the source structure, a second portion surrounded by the spacer layers, and a third portion below the second portion, and
wherein the first portion has a first width, the second portion has a second width smaller than the first width, and the third portion has a third width greater than the second width.
2 . The semiconductor device of claim 1 , wherein the third width is greater than the first width.
3 . The semiconductor device of claim 1 , wherein lower surfaces of the spacer layers are on a level lower than a level of a lower surface of the source structure.
4 . The semiconductor device of claim 1 , wherein a width of each of the spacer layers on an upper surface is smaller than a width on a bottom surface.
5 . The semiconductor device of claim 1 , wherein each of the spacer layers has a width of about 100 nm to about 250 nm.
6 . The semiconductor device of claim 1 , wherein the spacer layers include at least one of silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), and silicon oxynitride carbide (SiOCN).
7 . The semiconductor device of claim 1 , wherein, each of the contact plugs includes a side surface of the second portion, and the side surface of the second portion of each of the contact plugs has non-uniform inclination.
8 . The semiconductor device of claim 1 , wherein, in each of the contact plugs the first portion, the second portion, and the third portion are included in a single layer.
9 . The semiconductor device of claim 1 , wherein the spacer layers extend to the upper surface of the source structure and the spacer layers cover the upper surface of the source structure.
10 . The semiconductor device of claim 1 , wherein upper ends of the spacer layers are on a level which is a same level as or a lower level than a level of the upper surface of the source structure.
11 . The semiconductor device of claim 1 ,
wherein the second semiconductor structure further includes a through-via extending in an external side of the source structure in the first direction and the through-via is connected to one of the lower interconnection lines, and
wherein the through-via is on a same level as a level of the contact plugs, and the through-via has a shape different from a shape of the contact plugs.
12 . The semiconductor device of claim 11 ,
wherein the second semiconductor structure further includes an external-side insulating layer covering an external side surface of the source structure, the external-side insulating layer extending to an upper surface of the peripheral region insulating layer, and the external-side insulating layer including a same material as a material of the spacer layers, and
wherein the through-via penetrates the external-side insulating layer.
13 . The semiconductor device of claim 1 ,
wherein the second semiconductor structure further includes a ground via extending from a lower surface of the source structure in the first direction and the ground via is connected to one of the lower interconnection lines, and
wherein the ground via is integrated with the source structure.
14 . The semiconductor device of claim 13 , wherein, in each of the contact plugs the third portion overlaps the ground via in a second direction perpendicular to the first direction.
15 . The semiconductor device of claim 1 , wherein the source structure includes:
a plate layer on the peripheral region insulating layer;
a first horizontal conductive layer on the plate layer in the first region; and
a second horizontal conductive layer on the first horizontal conductive layer and the second horizontal conductive layer extending to the second region.
16 . A semiconductor device, comprising:
a substrate;
circuit devices on the substrate;
lower interconnection lines electrically connected to the circuit devices;
a peripheral region insulating layer covering the lower interconnection lines;
a source structure on the peripheral region insulating layer;
gate electrodes stacked on the source structure and spaced apart from each other in a first direction perpendicular to an upper surface of the source structure;
channel structures penetrating through the gate electrodes, the channel structures extending in the first direction, and each of the channel structures including a channel layer;
contact plugs penetrating through the gate electrodes and the source structure, the contact plugs extending in the first direction, and the contact plugs each connected to a portion of the lower interconnection lines; and
spacer layers between the contact plugs and the source structure, and the spacer layers including a material different from a material of the peripheral region insulating layer,
wherein each of the spacer layers has a first width on an upper surface and each of the spacer layers has a second width greater than the first width on a lower surface.
17 . The semiconductor device of claim 16 , wherein each of the contact plugs includes a first region in which a width thereof does not uniformly decrease downwardly, the first region being in a region of the contact plug surrounded by the spacer layers.
18 . The semiconductor device of claim 16 , wherein each of the contact plugs has a first diameter on a level of the upper surface of the source structure, each of the contact plugs has a second diameter smaller than the first diameter on a level of a lower surface of the source structure, and each of the contact plugs has a third diameter greater than the second diameter on a lower surface of each of the contact plugs.
19 . A data storage system, comprising:
a semiconductor storage device including
a substrate, circuit devices on the substrate,
lower interconnection lines electrically connected to the circuit devices,
a peripheral region insulating layer covering the lower interconnection lines,
a plate layer on the peripheral region insulating layer,
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer,
contact plugs penetrating through the gate electrodes and the plate layer, the contact plugs extending in the first direction, and each of the contact plugs connected to a portion of the lower interconnection lines,
spacer layers between the contact plugs and the plate layer and the spacer layers including a material different from a material of the peripheral region insulating layer, and
input/output pads electrically connected to the circuit devices,
wherein a controller is electrically connected to the semiconductor storage device through the input/output pad and the controller is configured to control the semiconductor storage device, and
wherein each of the contact plugs has a first width on a level of a lower surface of the plate layer, and each of the contact plugs has a second width greater than the first width on a lower surface of each of the contact plugs.
20 . The data storage system of claim 19 , wherein each of the spacer layers has a third width on an upper surface and each of the spacer layers has a fourth width greater than the third width on a lower surface.