Power amplifier circuit

1 . A power amplifier circuit comprising:

a first amplifier transistor comprising a base or gate configured to receive a first signal inputted, the first signal comprising one balanced signal, a collector or drain configured to output a first amplified signal generated by amplifying the first signal, and an emitter or source that is electrically connected to ground;

a second amplifier transistor comprising a base or gate configured to receive a second signal inputted, the second signal comprising a second balanced signal, a collector or drain configured to output a second amplified signal generated by amplifying the second signal, and an emitter or source that is electrically connected to the ground;

a first variable capacitance electrically coupled between the collector or drain of the second amplifier transistor and the base or gate of the first amplifier transistor; and

a second variable capacitance electrically coupled between the collector or drain of the first amplifier transistor and the base or gate of the second amplifier transistor,

wherein the first variable capacitance comprises a first capacitor and a first switch that are coupled in series with each other, and

wherein the second variable capacitance comprises a second capacitor and a second switch that are coupled in series with each other.

2 . The power amplifier circuit according to claim 1 , further comprising:

a second control circuit configured to control the first variable capacitance and the second variable capacitance based on an amount of a supply voltage supplied to the first amplifier transistor and the second amplifier transistor.

3 . The power amplifier circuit according to claim 1 , wherein

the first variable capacitance further comprises a third capacitor and a third switch that are coupled in series with each other and that are coupled in parallel with the first capacitor and the first switch, and

the second variable capacitance further comprises a fourth capacitor and a fourth switch that are coupled in series with each other and that are coupled in parallel with the second capacitor and the second switch.

4 . The power amplifier circuit according to claim 1 , further comprising:

a first control circuit configured to control the first variable capacitance and the second variable capacitance based on whether a third signal generated from the first amplified signal and the second amplified signal is greater or smaller than a first predetermined value.

5 . The power amplifier circuit according to claim 4 , wherein

the first control circuit comprises:

a wave detector circuit configured to generate a first voltage based on an amplitude of the third signal, and

a first comparator circuit configured to output a fourth signal of a level determined based on a result of comparing the first voltage with the first predetermined value to the first variable capacitance and the second variable capacitance.

6 . The power amplifier circuit according to claim 2 , wherein

the second control circuit comprises a second comparator circuit configured to output a fifth signal of a level determined based on a result of comparing the supply voltage with a second predetermined value to the first variable capacitance and the second variable capacitance.

7 . The power amplifier circuit according to claim 6 , wherein

the second control circuit further comprises a third comparator circuit configured to output a sixth signal of a level determined based on a result of comparing the supply voltage with a third predetermined value that is different from the second predetermined value to the first variable capacitance and the second variable capacitance.

8 . The power amplifier circuit according to of claim 7 , further comprising:

a third amplifier transistor in a stage before the first amplifier transistor and the second amplifier transistor.

9 . The power amplifier circuit according to claim 5 , further comprising:

a second comparator circuit configured to output a fifth signal of a level determined based on a result of comparing a supply voltage supplied to the first amplifier transistor and the second amplifier transistor with a second predetermined value; and

a third control circuit configured to control the first variable capacitance and the second variable capacitance based on the level of the fourth signal and the level of the fifth signal.

10 . The power amplifier circuit according to of claim 1 , further comprising:

a third amplifier transistor in a stage before the first amplifier transistor and the second amplifier transistor.

11 . The power amplifier circuit according to of claim 9 , further comprising:

a third amplifier transistor in a stage before the first amplifier transistor and the second amplifier transistor.

12 . The power amplifier circuit according to claim 3 , further comprising:

a first control circuit configured to control the first variable capacitance and the second variable capacitance based on whether a third signal generated from the first amplified signal and the second amplified signal is greater or smaller than a first predetermined value.

13 . The power amplifier circuit according to of claim 6 , further comprising:

a third amplifier transistor in a stage before the first amplifier transistor and the second amplifier transistor.

14 . The power amplifier circuit according to of claim 3 , further comprising:

a third amplifier transistor in a stage before the first amplifier transistor and the second amplifier transistor.

15 . The power amplifier circuit according to of claim 4 , further comprising:

a third amplifier transistor in a stage before the first amplifier transistor and the second amplifier transistor.

16 . The power amplifier circuit according to of claim 5 , further comprising:

a third amplifier transistor in a stage before the first amplifier transistor and the second amplifier transistor.

17 . The power amplifier circuit according to of claim 2 , further comprising:

a third amplifier transistor in a stage before the first amplifier transistor and the second amplifier transistor.