SEMICONDUCTOR PACKAGE HAVING WETTABLE FLANKS AND RELATED METHODS

1 . A method of forming a semiconductor package comprising:

coupling a plurality of die to a pad carrier, the pad carrier comprising a carrier and a plurality of pads;

wire bonding the plurality of die to the plurality of pads;

applying a mold compound over the plurality of die;

removing the carrier; and

singulating a plurality of semiconductor packages.

2 . The method of claim 1 , wherein each pad of the plurality of pads comprises an etch stop layer directly coupled to the carrier, a solderable layer directly coupled to the etch stop layer, and a wire bondable layer directly coupled to the solderable layer.

3 . The method of claim 1 , wherein the semiconductor package comprises a multi-chip module package.

4 . The method of claim 1 , wherein the plurality of pads form a plurality of wettable flanks in each semiconductor package of the plurality of semiconductor packages.

5 . The method of claim 1 , wherein the semiconductor package comprises a chip-on-lead package.

6 . A method of forming a semiconductor package comprising:

coupling a plurality of die to a pre-plated pad carrier, the pre-plated pad carrier comprising a metal carrier and a plurality of pre-plated pads;

wire bonding the plurality of die to the plurality of pre-plated pads;

applying a mold compound over the plurality of die;

removing the metal carrier; and

singulating a plurality of semiconductor packages;

wherein each pre-plated pad of the plurality of pre-plated pads comprises a solderable layer coupled between the metal carrier and a wire bondable layer.

7 . The method of claim 6 , wherein the wire bondable layer is directly coupled to the solderable layer.

8 . The method of claim 6 , wherein the wire bondable layer overhangs the solderable layer and forms a mold lock.

9 . The method of claim 6 , wherein the solderable layer of the plurality of pads is exposed on at least two sides of each semiconductor package of the plurality of semiconductor packages.

10 . The method of claim 6 , wherein each pre-plated pad further comprises an etch stop layer coupled between the solderable layer and the metal carrier.

11 . The method of claim 6 , wherein the metal carrier is removed through a grinding process.

12 . The method of claim 6 , wherein the metal carrier is removed through an etching process.

13 . The method of claim 6 , wherein the wire bondable layer overhangs the solderable layer on at least 3 sides and forms a mold lock.

14 . A method of forming a semiconductor package comprising:

forming a pre-plated pad carrier by:

patterning a first layer of photoresist coupled over a metal carrier;

electroplating a first metal layer over the metal carrier;

patterning a second layer of photoresist coupled over the first layer of photoresist;

electroplating a second metal layer over the first metal layer; and

removing both the first layer of photoresist and the second layer of photoresist, wherein the first metal layer and the second metal layer forms a plurality of pre-plated pads;

coupling a plurality of die to the plurality of pre-plated pads;

wire bonding the plurality of die to the plurality of pre-plated pads;

applying a mold compound over the plurality of die;

removing the metal carrier; and

singulating a plurality of semiconductor packages.

15 . The method of claim 14 , further comprising electroplating an etch stop layer directly to the metal carrier, wherein the first metal layer is electroplated over the etch stop layer.

16 . The method of claim 14 , wherein the second metal layer of the pre-plated pad carrier overhangs the first metal layer of the pre-plated pad carrier.

17 . The method of claim 14 , wherein the plurality of semiconductor packages are between 0.90 mm and 0.30 mm thick.

18 . The method of claim 14 , wherein the plurality of pre-plated pads form wettable flanks exposed on two sides of each semiconductor package of the plurality of semiconductor packages.

19 . The method of claim 14 , wherein the plurality of semiconductor packages comprise quad-flat no-leads packages.

20 . The method of claim 14 , wherein the second metal layer comprises one of silver or NiPdAu.