Storage I/O management unit for solid-state drives
An I/O memory management unit operates to provide hardware moderated restrictions on access to internal I/O device addresses of I/O devices eliminating the interposition of the operating system in such data transfers. As well as providing read/write permissions, the I/O memory management unit can perform address translation for virtualization and may be the combined with the functions of an IOMMU for managing physical addresses.
1. An I/O memory management unit for use in a computer architecture having a processor communicating with a main computer memory having memory addresses and an I/O device having I/O device addresses, the I/O memory management unit comprising circuitry operating to:
(a) receive from the I/O device an I/O device address previously sent to the I/O device in a request from the processor;
(b) communicate with a data structure held in the main computer memory to match the I/O device address to permission data authorizing or not authorizing access to the I/O device address;
(c) output the permission data to the I/O device;
(d) receive from the I/O device a memory address for data transfer with the I/O device;
(e) communicate with a second data structure held in the main computer memory to match the memory address to second permission data authorizing or not authorizing access to the memory address; and
(f) output the second permission data to the I/O device.
2. The I/O memory management unit of claim 1 wherein the I/O device is a solid-state drive holding data arranged in blocks and the I/O device addresses are block addresses.
3. The I/O memory management unit of claim 2 wherein the I/O device address is a virtual address and wherein the communication with the data structure provides a physical I/O device address different from the I/O device address, linked to the I/O device address and indicating a physical block of the solid-state drive associated with the I/O device address.
4. The I/O memory management unit of claim 2 wherein the I/O memory management unit further receives an application identifier and communicates with the data structure to match the I/O device address and the application identifier to I/O device address and application identifier linked permission data indicating a permission to access the I/O device address of the I/O device and used to provide the permission data to the I/O device.
5. The I/O memory management unit of claim 1 wherein the permission data is the existence of a matching entry in the data structure.
6. The I/O memory management unit of claim 1 wherein the permission data is a field in an existing data structure entry.
7. The I/O memory management unit of claim 1 wherein the I/O memory management unit further executes to:
communicate with a data structure cache holding portions of the data structure to match the I/O device address to I/O device address-linked permission data; and when there is a matching in the portions, provide the permission data from the data structure cache and otherwise provide the permission data from the data structure held in main computer memory.
8. The I/O memory management unit of claim 1 wherein the memory address is a virtual memory address and wherein the communication with the second data structure provides a physical memory address different from the virtual physical address, linked to the virtual memory address and indicating a physical address of the main memory associated with the virtual physical address.
9. The I/O memory management unit of claim 1 wherein the I/O memory management unit further executes to:
receive from the I/O device an address previously sent to the I/O device in a request from the processor including a file transfer bit indicating whether the address is an I/O device address or a memory address and reviews the data structure or second data structure depending on the file transfer bit.
10. The I/O memory management unit of claim 1 wherein the main computer memory is random access memory and the solid-state drive is nonvolatile solid-state memory.
11. A computer architecture comprising:
one or more electronic processors;
a main computer memory including solid-state memory holding an operating system and application program;
at least one solid-state drive accessible by the operating system using a file system;
a I/O memory management unit comprising an integrated circuit executing to:
(a) receive from an I/O device an I/O device address previously sent to the I/O device in a request from the one or more electronic processors;
(b) communicate with a data structure held in the main computer memory to match the I/O device address to permission data authorizing or not authorizing access to the I/O device address;
(c) outputting the permission data to the I/O device;
(d) receiving from the I/O device a memory address for data transfer with the I/O device;
(e) communicating with a second data structure held in the main computer memory to match the memory address to second permission data authorizing or not authorizing access to the memory address; and
(f) outputting the second permission data to the I/O device.
12. The computer architecture of claim 11 wherein the one or more processors communicates with the main computer memory over a memory bus and the processor communicates with the at least one solid-state drive over an I/O bus different from the memory bus.
13. The computer architecture of claim 11 wherein the I/O memory management unit further executes to convert virtual addresses from the one or more processors received over the memory bus to physical addresses of the main memory.
14. The computer architecture of claim 11 wherein the I/O device address is a virtual address and wherein the communication with the data structure provides a physical I/O device address different from the I/O device address, linked to the I/O device address and indicating a physical block of the at least one solid-state drive associated with the I/O device address.
15. A method of accessing an I/O device in a computer architecture having a processor communicating with a main computer memory having memory addresses and an I/O device having I/O device addresses, the method comprising:
(a) receiving from the I/O device an I/O device address previously sent to the I/O device in a request from the processor; and
(b) communicating with a data structure held in the main computer memory to match the I/O device address to permission data authorizing or not authorizing access to the I/O device address;
(c) outputting the permission data to the I/O device
(d) receiving from the I/O device a memory address for data transfer with the I/O device;
(e) communicating with a second data structure held in the main computer memory to match the memory address to second permission data authorizing or not authorizing access to the memory address; and
(f) outputting the second permission data to the I/O device.
16. The method of claim 15 wherein the I/O device address is a virtual address and wherein the communication with the data structure provides a physical I/O device address different from the I/O device address, linked to the I/O device address and indicating a physical block of a solid-state drive associated with the I/O device address.