Semiconductor devices having variously-shaped source/drain patterns
View Patent ↗A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.
1. A semiconductor device comprising:
a substrate;
a first fin, a second fin, a third fin and a fourth fin on the substrate;
a first isolation on the substrate;
a second isolation on the substrate and between the first fin and the second fin, the first fin between the first isolation and the second isolation;
a third isolation on the substrate and between the second fin and the third fin;
a fourth isolation on the substrate and between the third fin and the fourth fin;
a fifth isolation on the substrate, the fourth fin between the fourth isolation and the fifth isolation;
a first gate on the first through fourth fins and the first through fifth isolations;
a second gate on the first through fourth fins and the first through fifth isolations;
a first epitaxial source/drain on the first fin and between the first gate and the second gate;
a second epitaxial source/drain on the second fin and between the first gate and the second gate;
a third epitaxial source/drain on the third fin and between the first gate and the second gate;
a fourth epitaxial source/drain on the fourth fin and between the first gate and the second gate; and
a contact on the first through fourth epitaxial source/drain,
wherein the first, second, third and fourth epitaxial source/drains are merged into a merged epitaxial source/drain, and
wherein an upper surface of the merged epitaxial source/drain includes a first recess and a second recess.
2. The semiconductor device of claim 1 , wherein a depth of the first recess is different from a depth of the second recess.
3. The semiconductor device of claim 1 , wherein an upper surface of the third epitaxial source/drain is concave.
4. The semiconductor device of claim 1 , wherein a void is between the merged epitaxial source/drain, the second fin and the third fin.
5. The semiconductor device of claim 1 , further comprising:
a via on the contact; and
a wiring line on the via.
6. The semiconductor device of claim 1 , wherein the contact includes titanium, tantalum, tungsten, copper or aluminum.
7. A semiconductor device comprising:
a substrate;
a first fin, a second fin and a third fin on the substrate;
a first epitaxial source/drain on the first fin;
a second epitaxial source/drain on the second fin;
a third epitaxial source/drain on the third fin; and
a contact in contact with the first, second and third epitaxial source/drains,
wherein the first, second and third epitaxial source/drains are merged into a merged epitaxial source/drain,
wherein an upper surface of the merged epitaxial source/drain includes a first recess and a second recess,
wherein a depth of the first recess is different from a depth of the second recess.
8. The semiconductor device of claim 7 , further comprising:
a fourth fin on the substrate; and
a fourth epitaxial source/drain on the fourth fin,
wherein the merged epitaxial source/drain has a flat top surface that connects an uppermost portion of the third epitaxial source/drain to an uppermost portion of the fourth epitaxial source/drain.
9. The semiconductor device of claim 7 , wherein the depth of the second recess is less than the depth of the first recess.
10. The semiconductor device of claim 9 , wherein a width of a bottom of the second recess is greater than a width of a bottom of the first recess.
11. The semiconductor device of claim 9 , wherein a level of a bottom of the second recess is higher than a level of a bottom of the first recess.
12. The semiconductor device of claim 7 , wherein a void is between the merged epitaxial source/drain, the second fin and the third fin.
13. The semiconductor device of claim 7 , wherein the contact includes a first interposed portion in the first recess and a second interposed portion in the second recess,
wherein a height of the first interposed portion is different from a height of the second interposed portion.
14. The semiconductor device of claim 13 , wherein a width of a bottom of the first interposed portion is different from a width of a bottom of the second interposed portion.
15. A semiconductor device comprising:
a substrate;
a first fin, a second fin and a third fin on the substrate;
a first epitaxial source/drain on the first fin;
a second epitaxial source/drain on the second fin;
a third epitaxial source/drain on the third fin; and
a contact in contact with the first, second and third epitaxial source/drains,
wherein the first, second and third epitaxial source/drains are merged into a merged epitaxial source/drain,
wherein an upper surface of the merged epitaxial source/drain includes a first recess and a second recess,
wherein the contact includes a first interposed portion in the first recess and a second interposed portion in the second recess,
wherein a height of the first interposed portion is different from a height of the second interposed portion.
16. The semiconductor device of claim 15 , wherein a width of a bottom of the first interposed portion is different from a width of a bottom of the second interposed portion.
17. The semiconductor device of claim 15 , wherein the first interposed portion is between an uppermost portion of the first epitaxial source/drain and an uppermost portion of the second epitaxial source/drain,
wherein the second interposed portion is between the uppermost portion of the second epitaxial source/drain and an uppermost portion of the third epitaxial source/drain.
18. The semiconductor device of claim 15 , further comprising:
a fourth fin on the substrate; and
a fourth epitaxial source/drain on the fourth fin,
wherein the merged epitaxial source/drain has a flat top surface that connects an uppermost portion of the third epitaxial source/drain to an uppermost portion of the fourth epitaxial source/drain.
19. The semiconductor device of claim 18 , wherein a level of bottom of the first interposed portion and a level of bottom of the second interposed portion are lower than a level of the flat top surface.
20. The semiconductor device of claim 18 , wherein a level of an uppermost portion of the first epitaxial source/drain, a level of an uppermost portion of the second epitaxial source/drain and a level of the flat top surface are same.