IP Library › Granted Patent US 12,292,792
Granted Patent B1
US 12,292,792 · App. 18/199,456 · Granted May 6, 2025

Erasure coding techniques for flash memory

Inventors: Robert Lercari (Thousand Oaks, CA); Craig Robertson (Simi Valley, CA); Mike Jadon (Manhattan Beach, CA)
Assignee: Radian Memory Systems, LLC
G06F11/1068G06F9/30029G06F11/0772G06F11/0784G06F11/3037
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Quick Facts
Patent No.
US 12,292,792
App. No.
18/199,456
Granted
May 6, 2025
Kind
B1
Abstract

This disclosure provides a memory controller for asymmetric non-volatile memory, such as flash memory, and related host and memory system architectures. The memory controller is configured to automatically generate and transmit redundancy information to a destination, e.g., a host or another memory drive, to provide for cross-drive redundancy. This redundancy information can be error correction (EC) information, which is linearly combined with similar information from other drives to create “superparity.” If EC information is lost for one drive, it can be rebuilt by retrieving the superparity, retrieving or newly generating EC information for uncompromised drives, and linearly combining these values. In one embodiment, multiple error correction schemes are used, including a first intra-drive scheme to permit recovery of up to x structure-based failures, and the just-described redundancy scheme, to provide enhanced security for greater than x structure-based failures.

Claims (55)

1. A storage system comprising:

a host system, having at least one processor; and

one or more storage drives;

wherein:

a given one of the storage drives comprises a memory controller, channels, and, on each of the channels, flash memory dies;

the host system is configured to send a discovery command to the memory controller, and the memory controller is configured to responsively report, to the host system, a number of the channels and a number of the flash memory dies;

the host system is configured to use the reported number of channels and the reported number of flash memory dies to select a number of the channels that are to be associated with a virtual memory unit, and a number of the flash memory dies that are to be associated with the virtual unit, and to send the host-selected numbers to the given one of the storage drives;

the host system is configured to send write requests addressed to the virtual storage unit, with write data;

the memory controller is configured to service each of the write requests by identifying a subset of the flash memory dies which correspond to the host-selected numbers, and by issuing commands to the subset of the flash memory dies to store the write data; and

the memory controller is configured to calculate error correction information for the write data according to a computation formula that varies according to at least one of the host-selected numbers.

2. The storage system of claim 1 wherein:

the virtual memory unit is a first virtual memory unit, the host-selected numbers are first numbers, the write requests are first write requests, and the subset is a first subset;

the host system is configured to use the reported number of channels and the reported number of flash memory dies to select a second number of the channels that are to be associated with a second virtual memory unit, and a second number of the flash memory dies that are to be associated with the second virtual memory unit, and to send the second host-selected numbers specific to the second virtual memory unit to the given one of the storage drives;

the host system is configured to send second write requests addressed to the second virtual storage unit, with second write data;

the memory controller is configured to service each of the second write requests by identifying a second subset of the flash memory dies which correspond to the second host-selected numbers, and by issuing commands to the second subset of the flash memory dies to store the second write data; and

the memory controller is configured to calculate error correction information for the second write data according to a computation formula that varies according to at least one of the second host-selected numbers.

3. The storage system of claim 2 wherein the flash memory dies in the first subset and the flash memory dies in the second subset are mutually-exclusive to one another.

4. The storage system of claim 2 wherein the first host-selected numbers can be chosen by the host to be selectively different than the second host-selected numbers.

5. The storage system of claim 2 wherein the memory controller is further configured to perform at least one of wear leveling and garbage collection on an independent basis for each of the first virtual memory unit and the second virtual memory unit.

6. The storage system of claim 5 wherein a stored setting corresponding to the at least one of wear leveling and garbage collection causes a trigger for the at least one of wear leveling or garbage collection to be selectively different for the first virtual memory unit than for the second virtual memory unit, as a function of the stored setting.

7. The storage system of claim 2 wherein:

the host system is configured to issue read requests to the given one of the storage drives, to read the write data;

the memory controller comprises translation circuitry which is configured to translate read addresses provided with the read requests into corresponding memory addresses; and

the way in which read addresses are mapped to corresponding memory address differs for the first virtual memory unit than for the second virtual memory unit in a least one of a number of the sequential read addresses of data before a plane designation is changed in the corresponding memory addresses, a number of sequential read addresses before a channel designation is changed in the corresponding memory addresses, a number of sequential read addresses before a die designation is changed in the corresponding memory addresses, a number of sequential read addresses before an erase unit designation is changed in the corresponding memory addresses, and a number of sequential read addresses before a page designation is changed in the corresponding memory addresses.

8. The storage system of claim 2 wherein:

the memory controller comprises address generation circuitry which is configured to generate memory addresses in fulfillment of the write requests; and

the manner in which the memory addresses are generated differs for the first virtual memory unit than for the second virtual memory unit in a least one of a number of the sequential writes of data before a plane designation is changed in the corresponding memory addresses, a number of sequential writes of data before a channel designation is changed in the corresponding memory addresses, a number of sequential writes of data before a die designation is changed in the corresponding memory addresses, a number of sequential writes of data before an erase unit designation is changed in the corresponding memory addresses, and a number of sequential writes of data before a page designation is changed in the corresponding memory addresses.

9. The storage system of claim 1 wherein:

the host system is configured to issue read requests to the given one of the storage drives, to read the write data;

the memory controller comprises translation circuitry which is configured to translate read addresses provided with the read requests into corresponding physical memory addresses; and

the translation circuitry is configured to subdivide the read addresses into first and second address portions, is configured to identify the virtual memory unit from the first address portion, and is configured to identify an offset address to serve as an operand for read commands issued by the memory controllers to the subset of flash memory dies from the second address portion.

10. The storage system of claim 9 wherein the first and second address portions comprise respective, non-overlapping bit fields of the read addresses.

11. The storage system of claim 9 wherein the translation circuitry is configured to identify a specific address translation table dedicated to the virtual memory unit according to the first address portion and is configured to obtain the corresponding physical memory addresses from the specific address translation table.

12. The storage system of claim 1 wherein the memory controller comprises memory address generation circuitry, wherein the flash memory dies in the subset comprise planes, erase units and pages, and wherein the memory address generation circuitry is configured to receive a host-specified setting for the virtual memory unit, the host-specified setting comprising at least one of a number of the sequential writes of data before a generated plane address is to be changed, a number of sequential writes before a generated channel address is to be changed, a number of sequential writes of data before a generated die address is to be changed, a number of sequential writes of data before a generated erase unit address is to be changed, and a number of sequential writes of data before a generated page address is to be changed.

13. The storage system of claim 1 wherein the virtual memory unit is associated with two or more subdivisions, wherein the memory controller is configured to store information representing the two or more subdivisions, and wherein the memory controller is configured to transmit, to the one host system, information, representing the two or more subdivisions.

14. The storage system of claim 13 wherein the host system is configured to transmit a query to the given one of the storage drives and wherein the memory controller is configured to responsively:

identify a specific one of the two or more subdivisions; and

transmit to the at least one host processor an identifier for the specific one of the two or more subdivisions.

15. The storage system of claim 14 wherein the host system is configured to transmit to the given one of the storage drives, in dependence on the identifier, a write request in a manner, directed to the specific one of the two or more subdivisions.

16. The storage system of claim 13 wherein:

the flash memory dies comprise physical erase units;

the memory controller is configured to associate each of the two or more subdivisions with a respective set of one or more of the physical erase units; and

the information transmitted to the host system representing the two or more subdivisions comprises information representing at least one of a number of the two or more subdivisions and a size of each of the two or more subdivisions.

17. The storage system of claim 16 wherein information representing at least one of a number of the two or more subdivisions and a size of each of the two or more subdivisions information comprises information representing a capacity of each of the two or more subdivisions, wherein the capacity of each of two or more subdivisions is capable of being a non-power-of-two number of logical block addresses.

18. The storage system of claim 16 wherein the host system is further configured to transmit a maintenance command to the given one of the storage drives, in a manner addressed to a specific one of the two or more subdivisions, and wherein the memory controller is configured to responsively control the erasure of at least one erase unit in the respective set associated with the specific one of the two or more subdivisions.

19. The storage system of claim 16 wherein at least one of the flash memory dies comprises planes, and wherein the respective set associated with specific one of the two or more subdivisions comprises two or more erase units, wherein the two or more of the erase units are associated with different ones of the planes.

20. The storage system of claim 13 wherein the memory controller is further configured to track metadata specific to each of the two or more subdivisions.

21. The storage system of claim 20 wherein the host system is configured to query the given one of the storage drives for information dependent on the stored metadata, and wherein the memory controller is responsively configured to transmit, to the host system, information dependent on the metadata.

22. The storage system of claim 21 wherein the information transmitted to the host system dependent on the metadata indicates an extent to which the respective set associated with the specific one of the two or more subdivisions can continue to receive writes.

23. The storage system of claim 1 wherein the subset of the channels and the flash memory dies which is mapped to the virtual memory unit is selected by the memory controller of the given one of the drives, so as to correspond to the host-selected numbers.

24. The storage system of claim 1 wherein the computation formula varies according to the host-selected number of the channels.

25. The storage system of claim 1 wherein the computation formula varies according to the host-selected number of the flash memory dies.

26. The storage system of claim 1 wherein the memory controller is configured to store the error correction information in the given one of the storage drives in association with the virtual memory unit.

27. The storage system of claim 1 wherein the memory controller of the given one of the drives is configured to directly transmit the error correction information from the given one of the storage drives to another one of the storage drives, without transmitting the error correction information to the host system, and wherein the other one of the storage drives is configured to store error correction information dependent on the error correction information received from the memory controller without transmitting the error correction information to the host system.

28. The storage system of claim 1 wherein the memory controller is configured to transmit the error correction information from the given one of the storage drives to the host system, and wherein the host system is configured to responsively store error correction data in a host-selected storage location in one of the one or more storage drives, the error correction data being dependent on the error correction information received from the memory controller.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2024
From: RADIAN MEMORY SYSTEMS, INC.
To: RADIAN MEMORY SYSTEMS LLC
Reel/Frame 067471/0240 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2023
From: LERCARI, ROBERT; ROBERTSON, CRAIG; JADON, MIKE
To: RADIAN MEMORY SYSTEMS, INC.
Reel/Frame 063708/0329 →
Continuity (2)
Continuation 17498629 · Oct 11, 2021
Continuation 16707934 · Dec 9, 2019
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