Data storage apparatus and apparatus and method for controlling nonvolatile memories
According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.
1. A data storage apparatus comprising:
channel controllers configured to control data input to and output from a plurality of nonvolatile memories, each nonvolatile memory associated with one of a plurality of channels;
an encoder configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories; and
a data controller configured to manage the encoded data in units of logical blocks when the channel controllers write the encoded data in parallel to the channels, and to allocate, for each logical block, parity data contained in the encoded data to planes of a select one of the plurality of channels, wherein the data controller is configured to allocate a same amount of data to the planes of the select channel in each logical block.
2. The data storage apparatus of claim 1 , further comprising a decoder configured to perform an error detection and correction process on the encoded data read from the channel controllers.
3. The data storage apparatus of claim 2 , wherein the decoder is configured to receive location data containing a channel number and a plane number that indicate positional relation between the logical block and the encoded data, while receiving the encoded data transferred from the data controller in the error detection/correction process.
4. The data storage apparatus of claim 1 , wherein the data controller is configured to associate source data, from which the encoded data is generated, with degree data and location data, both contained in the parity data, and to allocate the source data, in a logical block, to planes of channels other than the channel storing the parity data.
5. A memory control apparatus for use in a data storage apparatus comprising:
channel controllers configured to control data input to and output from a plurality of nonvolatile memories, each nonvolatile memory associated with one of a plurality of channels;
an encoder configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories; and
a data controller configured to manage the encoded data in units of logical blocks when the channel controllers write the encoded data in parallel to the channels, and to allocate, for each logical block, parity data contained in the encoded data to planes of a select one of the plurality of channels, wherein the data controller is configured to allocate a same amount of data to the planes of the select channel in each logical block.
6. The memory control apparatus of claim 5 , further comprising a decoder module configured to perform an error detection and correction process on the encoded data read from the channel controllers.
7. The memory control apparatus of claim 6 , wherein the decoder is configured to receive location data containing a channel number and a plane number that indicate positional relation between the logical block and the encoded data, while receiving the encoded data transferred from the data controller in the error detection/correction process.
8. The memory control apparatus of claim 5 , wherein the data controller is configured to associate source data, from which the encoded data is generated, with degree data and location data, both contained in the parity data, and to allocate the source data, in a logical block, to planes of channels other than the channel storing the parity data.
9. A method of controlling memories, for use in a data storage apparatus comprising a plurality of nonvolatile memories associated with a plurality of channels, the method comprising:
generating encoded data for an interchannel error correction process using data stored in each of the nonvolatile memories;
managing the encoded data in units of logical blocks when a plurality of channel controllers write the encoded data in parallel to the channels, and allocating, for each logical block, parity data contained in the encoded data to planes of a select one of the plurality of channels; and
allocating a same amount of data to the planes of the select channel in each logical block.
10. The method of claim 9 , further comprising performing an error detection and correction process on the encoded data read from the channels.
11. The method of claim 10 , further comprising receiving location data containing a channel number and a plane number that indicate positional relation between the logical block and the encoded data, while receiving the encoded data transferred from the channels in the error detection/correction process.
12. The method of claim 9 , further comprising:
associating source data, from which the encoded data is generated, with degree data and location data, both contained in the parity data; and
allocating the source data, in a logical block, to planes of channels other than the channel storing the parity data.