Semiconductor device
View Patent ↗A semiconductor device includes a substrate. A first channel pattern is disposed on the substrate. The first channel pattern includes a first side and a second side opposite to each other in a first direction. A first gate electrode is disposed on the first side of the first channel pattern. A first source/drain electrode is disposed on the first side of the first channel pattern. A second source/drain electrode is disposed on the second side of the first channel pattern. The first gate electrode overlaps the second source/drain electrode in the first direction.
1 . A semiconductor device comprising:
a substrate;
a first channel pattern disposed on the substrate, the first channel pattern including a first side and a second side opposite to each other in a first direction;
a first gate electrode disposed on the first side of the first channel pattern;
a first source/drain electrode disposed on the first side of the first channel pattern; and
a second source/drain electrode disposed on the second side of the first channel pattern,
wherein the first gate electrode overlaps the second source/drain electrode in the first direction,
wherein the first channel pattern is spaced apart from the substrate in a second direction perpendicular to the first direction.
2 . The semiconductor device of claim 1 , further comprising:
a second gate electrode disposed on the second side of the first channel pattern.
3 . The semiconductor device of claim 2 ,
wherein the first gate electrode is connected to the second gate electrode.
4 . The semiconductor device of claim 2 ,
wherein the second gate electrode overlaps the first source/drain electrode in the first direction.
5 . The semiconductor device of claim 1 , further comprising:
a second gate electrode disposed on the first side of the first channel pattern,
wherein the first source/drain electrode is disposed between the first gate electrode and the second gate electrode in a second direction that crosses the first direction.
6 . The semiconductor device of claim 5 , further comprising:
a third source/drain electrode disposed on the second side of the first channel pattern,
wherein the third source/drain electrode overlaps the second gate electrode in the first direction.
7 . The semiconductor device of claim 1 , further comprising:
a second channel pattern disposed on the substrate, the second channel pattern including a third side and a fourth side opposite to each other in the first direction; and
a third source/drain electrode disposed on the fourth side of the second channel pattern,
wherein the third side of the second channel pattern faces the first side of the first channel pattern, and
the first gate electrode and the first source/drain electrode are disposed between the first channel pattern and the second channel pattern in the first direction.
8 . The semiconductor device of claim 7 ,
wherein the first gate electrode overlaps the third source/drain electrode in the first direction.
9 . The semiconductor device of claim 1 ,
wherein the second source/drain electrode is connected to a power line.
10 . A semiconductor device comprising:
a substrate;
a first source/drain electrode disposed on the substrate, the first source/drain electrode extending in a first direction;
a second source/drain electrode disposed on the substrate, the second source/drain electrode extending in the first direction;
a first channel pattern that is spaced apart from the substrate in a second direction perpendicular to the first direction, the first channel pattern is disposed between the first source/drain electrode and the second source/drain electrode;
a second channel pattern that is spaced apart from the first channel pattern in the first direction, the second channel pattern is disposed between the first source/drain electrode and the second source/drain electrode; and
a first gate electrode disposed on the first channel pattern and the second channel pattern and extending in the first direction, the first gate electrode is spaced apart from the first source/drain electrode in the second direction crossing the first direction, and overlaps the first source/drain electrode in the second direction,
wherein the second source/drain electrode is spaced apart from the first gate electrode in a third direction that crosses the first and second directions, and overlaps the first gate electrode in the third direction.
11 . The semiconductor device of claim 10 , further comprising:
a second gate electrode disposed on the first channel pattern and the second channel pattern and extending in the first direction,
wherein the second gate electrode is spaced apart from the second source/drain electrode in the second direction, and overlaps the second source/drain electrode in the second direction, and
the second gate electrode is spaced apart from the first source/drain electrode in the third direction, and overlaps the first source/drain electrode in the third direction.
12 . The semiconductor device of claim 11 ,
wherein the first gate electrode is connected to the second gate electrode.
13 . The semiconductor device of claim 10 , further comprising:
a second gate electrode disposed on the first channel pattern, the second gate electrode is spaced apart from the second source/drain electrode in the third direction; and
a third source/drain electrode disposed on the first channel pattern, the third source/drain electrode is spaced apart from the second gate electrode in the second direction and overlaps the second gate electrode in the second direction,
wherein the second source/drain electrode is disposed between the first gate electrode and the second gate electrode.
14 . The semiconductor device of claim 10 , further comprising:
a third channel pattern spaced apart from the first channel pattern in the second direction; and
a third source/drain electrode disposed on the third channel pattern,
wherein the third channel pattern is disposed between the first gate electrode and the third source/drain electrode, and
the third source/drain electrode overlaps the first gate electrode and the first source/drain electrode in the second direction.
15 . The semiconductor device of claim 14 , wherein:
the second source/drain electrode is disposed between the first channel pattern and the third channel pattern; and
the second source/drain electrode does not overlap the first source/drain electrode and the third source/drain electrode in the second direction.
16 . A semiconductor device comprising:
a substrate;
a first channel pattern that is spaced apart from the substrate in a second direction perpendicular to the first direction, the first channel pattern includes an upper side and a lower side opposite to each other in a first direction, the lower side of the first channel pattern facing the substrate;
a first gate electrode disposed on the upper side of the first channel pattern;
a first source/drain electrode disposed on the upper side of the first channel pattern, and spaced apart from the first gate electrode in the second direction perpendicular to the first direction;
a second source/drain electrode disposed on the lower side of the first channel pattern and overlapping the first gate electrode in the first direction;
a second channel pattern disposed on the first gate electrode and the first source/drain electrode, the second channel pattern including an upper side and a lower side spaced apart from each other in the first direction, the lower side of the second channel pattern facing the upper side of the first channel pattern; and
a third source/drain electrode disposed on the upper side of the second channel pattern and overlapping the first gate electrode in the first direction.
17 . The semiconductor device of claim 16 , further comprising:
a second gate electrode disposed on the upper side of the second channel pattern and spaced apart from the third source/drain electrode in the second direction,
wherein the second gate electrode overlaps the first source/drain electrode in the first direction, and
the second gate electrode is connected to the first gate electrode.
18 . The semiconductor device of claim 16 , further comprising:
a second gate electrode disposed between the upper side of the first channel pattern and the lower side of the second channel pattern, the second gate electrode is spaced apart from the first source/drain electrode in the second direction,
wherein the first source/drain electrode is disposed between the first gate electrode and the second gate electrode.