Modular interconnects for gate-all-around transistors
A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.
1. A device, comprising:
a first conductive domain coupled to a first conductive ring in a first plane;
a second conductive domain coupled to a second conductive ring in a second plane that is substantially parallel to the first plane, the first and second conductive rings being coaxial;
a nanowire coupling the first and second conductive rings, the nanowire extending in a first direction that is transverse to the first and second planes; and
a via extending in a second direction that is transverse to the first and second planes, at least a portion of the via extending from the first conductive domain to the second conductive domain.
2. The device of claim 1 , wherein the first direction is substantially parallel to the second direction.
3. The device of claim 1 , wherein the first and second conductive domains are in the shape of radial sectors.
4. The device of claim 3 , wherein the first and second conductive domains further include a plurality of extension spokes, and a via landing pad, an extension spoke of the plurality of extension spokes coupled to the via landing pad.
5. The device of claim 1 , wherein the first and second conductive domains are metallic.
6. The device of claim 1 , wherein the first and second conductive domains are made of a semiconducting material.
7. The device of claim 1 , wherein the nanowire includes a switch.
8. The device of claim 1 , wherein the nanowire includes a channel of a transistor.
9. The device of claim 8 , wherein a portion of the nanowire is surrounded by a coaxial transistor gate.
10. The device of claim 1 , wherein each of the first and second conductive rings is aligned with a terminal of a transistor.
11. A device, comprising:
a nanowire extending along an axis;
a first planar disc extending in a first plane that is transverse to the axis and including a first conductive region coupled to a first conductive ring centered around the axis; and
a second planar disc extending in a second plane that is substantially parallel to the first plane and including a second conductive region coupled to a second conductive ring centered around the axis.
12. The device of claim 11 , further comprising a via extending in a direction substantially parallel to the axis and coupling the first and second conductive region.
13. The device of claim 11 , wherein the first and second conductive region are radial sectors of the first and second planar discs, respectively.
14. The device of claim 11 , wherein the first conductive region further includes a plurality of extensions radiating outward from the axis, each extension of the plurality of extensions coupled to a via landing pad.
15. The device of claim 11 , wherein the first and second conductive regions are metallic.
16. The device of claim 11 , wherein the first and second conductive regions are made of a semiconducting material.
17. A method, comprising:
forming a nanowire extending along an axis;
forming a first planar disc extending in a first plane that is transverse to the axis and including a first conductive region coupled to a first conductive ring centered around the axis; and
forming a second planar disc extending in a second plane that is substantially parallel to the first plane and including a second conductive region coupled to a second conductive ring centered around the axis.
18. The method of claim 17 , further comprising forming a via extending in a direction that is substantially parallel to the axis and coupling the first and second conductive region.
19. The method of claim 17 , further comprising forming a channel in the nanowire.
20. The method of claim 17 , further comprising forming a coaxial transistor gate around a portion of the nanowire.