Methods for 3D-integrating photonic chipsets by vertical assembly of lasers and passive components
A method for making a vertically arranged array of edge-emitting lasers comprises: obtaining semiconductor chips that are laser diodes or semiconductor optical amplifiers; coating each of the semiconductor chips with a thermally conductive dielectric material; bonding the semiconductor chips onto a carrier wafer, such that the semiconductor chips are vertically aligned; coating the semiconductor chips with an electroplating seed material; obtaining a body wafer having lithographically defined and passivated openings; positioning the body wafer and the carrier wafer to match the openings; electroplating a metal-containing material onto the seed material to fill open space; demounting the body wafer from the carrier wafer; etching excess material from the body wafer; and patterning metal regions in electrical contact with the semiconductor chips. A vertically arranged array of edge-emitting lasers is fabricated and is capable of emitting laser light parallel to the semiconductor chips and perpendicular to the plane of the body wafer.
1 . A method for making a vertically arranged array of edge-emitting lasers, said method comprising:
(a) obtaining a plurality of semiconductor chips, wherein said semiconductor chips are laser diodes or semiconductor optical amplifiers;
(b) coating each of said semiconductor chips on multiple sides with a thermally conductive dielectric material;
(c) bonding said semiconductor chips onto a carrier wafer at selected locations, wherein said semiconductor chips are vertically aligned relative to a surface of said carrier wafer;
(d) coating each of said semiconductor chips with an electroplating seed material;
(e) obtaining a body wafer having lithographically defined and passivated openings within a plane of said body wafer;
(f) positioning said body wafer and said carrier wafer to match said lithographically defined and passivated openings with said semiconductor chips;
(g) electroplating a metal-containing material onto said electroplating seed material to fill open space between said semiconductor chips and said lithographically defined and passivated openings;
(h) demounting said body wafer from said carrier wafer;
(i) etching excess material, if any, from said body wafer; and
(j) patterning a plurality of metal regions in electrical contact with said plurality of semiconductor chips,
thereby generating a vertically arranged array of edge-emitting lasers that is capable of emitting laser light parallel to said semiconductor chips and perpendicular to said plane of said body wafer.
2 . The method of claim 1 , wherein said semiconductor chips are fabricated from a semiconductor selected from the group consisting of GaAs, InP, GaSb, GaN, InGaN, AlGaN, AlGaInP, GaInP, GaAlAs, InGaAs, InGaAsP, GaInAsSb, and combinations thereof.
3 . The method of claim 1 , wherein said semiconductor chips are capable of emitting or amplifying ultraviolet laser light, visible laser light, infrared laser light, or a combination thereof.
4 . The method of claim 1 , wherein said semiconductor chips are each configured to emit or amplify at a single light wavelength.
5 . The method of claim 1 , wherein said semiconductor chips are collectively configured to emit or amplify at multiple light wavelengths.
6 . The method of claim 1 , wherein said thermally conductive dielectric material is selected from the group consisting of aluminum nitride, boron nitride, tantalum oxide, beryllium oxide, aluminum oxide, and combinations thereof.
7 . The method of claim 1 , wherein step (b) comprises coating each of said semiconductor chips on five sides with said thermally conductive dielectric material.
8 . The method of claim 1 , wherein step (c) utilizes an adhesive for said bonding.
9 . The method of claim 8 , wherein said adhesive is selected from the group consisting of polyimide, cyanoacrylate, acrylic, polyepoxides, polyethylene, polystyrene, ceramics, benzocyclobutene, parylene, and combinations thereof.
10 . The method of claim 1 , wherein said body wafer is fabricated from a body-wafer material selected from the group consisting of silicon, silicon carbide, germanium, gallium nitride, aluminum nitride, gallium oxide, silica, alumina, and combinations thereof.
11 . The method of claim 1 , wherein said carrier wafer is fabricated from a carrier-wafer material selected from the group consisting of silicon, silicon carbide, germanium, gallium nitride, aluminum nitride, gallium oxide, silica, alumina, and combinations thereof.
12 . The method of claim 1 , wherein said electroplating seed material is selected from the group consisting of copper, ruthenium, molybdenum, cobalt, titanium, platinum, gold, silver, nickel, chromium, aluminum, tantalum nitride, and combinations thereof.
13 . The method of claim 1 , wherein step (d) comprises coating each of said semiconductor chips on five sides with said electroplating seed material.
14 . The method of claim 1 , wherein said lithographically defined and passivated openings are characterized by an average cavity length, and wherein said vertically arranged array of edge-emitting lasers is characterized by an average array pitch that is less than said average cavity length in at least one planar dimension.
15 . The method of claim 1 , wherein step (e) comprises obtaining a starting body wafer, etching said starting body wafer to create etched openings, and then passivating said etched openings to create said lithographically defined and passivated openings.
16 . The method of claim 15 , wherein said passivating utilizes (i) native oxidation of said etched openings, (ii) deposition of an oxide layer onto said etched openings, and/or (iii) deposition of a nitride layer onto said etched openings.
17 . The method of claim 1 , wherein said metal-containing material in step (g) is selected from the group consisting of copper, ruthenium, molybdenum, cobalt, titanium, gold, silver, nickel, aluminum, indium, tin, and combinations thereof.
18 . The method of claim 1 , wherein said metal-containing material is chemically the same as said electroplating seed material.
19 . The method of claim 1 , wherein said metal-containing material is chemically different than said electroplating seed material.
20 . The method of claim 1 , wherein step (i) comprises etching excess thermally conductive dielectric material.
21 . The method of claim 1 , wherein step (i) comprises etching excess electroplating seed material.
22 . The method of claim 1 , wherein step (i) comprises etching excess metal-containing material.
23 . The method of claim 1 , wherein step (i) comprises etching said excess material from the top side of said body wafer that was previously in contact with said carrier wafer prior to step (h).
24 . The method of claim 1 , wherein said metal regions in step (j) contain a metal selected from the group consisting of copper, nickel, titanium, platinum, palladium, rhodium, gold, silver, and combinations thereof.
25 . The method of claim 1 , wherein said vertically arranged array of edge-emitting lasers is a two-dimensional vertically arranged array of edge-emitting lasers.
26 . The method of claim 1 , wherein said vertically arranged array of edge-emitting lasers is a three-dimensional vertically arranged array of edge-emitting lasers.
27 . The method of claim 1 , wherein said method further comprises stacking passive photonic elements along with said vertically arranged array of edge-emitting lasers, to form a modular photonic system.
28 . The method of claim 27 , wherein multiple vertically arranged arrays of edge-emitting lasers are stacked within said modular photonic system.
29 . The method of claim 1 , wherein said method further comprises packaging multiple vertically arranged arrays of edge-emitting lasers with optical components and drive electronics, to form an interposer platform.
30 . The method of claim 1 , wherein said method further comprises packaging multiple vertically arranged arrays of edge-emitting lasers with optical components and drive electronics, to form a photonic chipset.