Digital compute hardware for efficient element-wise and cross-vector maximum operations
View Patent ↗A system for efficient element-wise and cross-vector maximum operations. One example system includes an input bus, an output bus, and a memory configured to store N/K elements of an N-element vector in a corresponding row of the memory. A K-wide FMAX( ) comparator has a first set of K-wide inputs of the K-wide FMAX( ) comparator coupled to a read port of the memory and a second set of K-wide inputs of the K-wide FMAX( ) comparator coupled to the input bus, and a set of K-wide outputs of the K-wide FMAX( ) comparator coupled to a write port of the memory. A tree of FMAX( ) comparators comprises an input and an output, the input of the tree coupled to the set of K-wide outputs of the K-wide FMAX( ) comparator and the output of the tree coupled to the output bus.
1 . An apparatus comprising:
an input bus;
an output bus;
a memory configured to store K elements of an N-element vector in a corresponding row of the memory, the memory having a read port and a write port;
a K-wide FMAX( ) comparator, the K-wide FMAX( ) comparator having a first set of K-wide inputs coupled to the read port of the memory and a second set of K-wide inputs coupled to the input bus, the K-wide FMAX( ) comparator having a set of K-wide outputs coupled to the write port of the memory; and
a tree of FMAX( ) comparators, the tree having an input and an output, the input of the tree being coupled to the set of K-wide outputs of the K-wide FMAX( ) comparator and the output of the tree being coupled to the output bus.
2 . The apparatus of claim 1 , further comprising an OUT register, an input of the OUT register coupled to the set of K-wide outputs of the K-wide FMAX( ) comparator and an output of the OUT register coupled to the write port of the memory.
3 . The apparatus of claim 2 , further comprising a controller coupled to the OUT register and configured to initialize the OUT register, for an initial comparison operation, to a scalar value representing a largest-negative value capable of being stored in the OUT register.
4 . The apparatus of claim 1 , further comprising an OUT register, an input of the OUT register coupled to the output of the tree and an output of the OUT register coupled to the output bus.
5 . The apparatus of claim 1 , wherein the memory is a dedicated local memory.
6 . The apparatus of claim 5 , wherein the dedicated local-memory is a static random-access memory.
7 . A system comprising:
a memory having a read port and a write port;
an interconnection network; and
a plurality of MAX compute circuits coupled to the interconnection network, each MAX compute circuit assigned a corresponding portion of each of a plurality of arriving vectors;
wherein each MAX compute circuit is configured to:
receive the corresponding portion of each arriving vector as a time-multiplexed set of sequences of elements,
store each of the sequence of elements in a row of the memory,
perform a parallel MAX( ) operation between a subsequent sequence of elements and a corresponding sequence of elements stored within the memory for a corresponding point in the time-multiplexed set,
store a resulting sequence of elements into the memory, and
output a final resulting sequence of elements from the memory;
wherein each MAX compute circuit comprises:
a controller configured to control a flow of data through the corresponding MAX compute circuit;
an input bus;
an output bus;
a K-wide FMAX( ) comparator, a first set of K-wide inputs of the K-wide FMAX( ) comparator coupled to the read port of the memory and a second set of K-wide inputs of the K-wide FMAX( ) comparator coupled to the input bus, and a set of K-wide outputs of the K-wide FMAX( ) comparator coupled to the write port of the memory; and
a tree of FMAX( ) comparators, the tree comprising an input and an output, the input of the tree coupled to the set of K-wide outputs of the K-wide FMAX( ) comparator and the output of the tree coupled to the output bus, wherein the memory is configured to store N/K elements of an N-element vector in a corresponding row of the memory.
8 . The system of claim 7 , each MAX compute circuit further comprising an OUT register, an input of the OUT register coupled to the set of K-wide outputs of the K-wide FMAX( ) comparator and an output of the OUT register coupled to the write port of the memory.
9 . The system of claim 8 , wherein a controller is configured to initialize the OUT register, for an initial comparison operation, to a scalar value representing a largest-negative value capable of being stored in the OUT register.
10 . The system of claim 7 , each MAX compute circuit further comprising an OUT register, an input of the OUT register coupled to the output of the tree and an output of the OUT register coupled to the output bus.
11 . A system comprising:
an interconnection network;
an OUT register comprising an output;
a plurality of MAX compute circuits coupled to the interconnection network, each MAX compute circuit assigned a corresponding portion of each of one or more arriving vectors;
wherein each MAX compute circuit is configured to:
receive the corresponding portion of each arriving vector as a time-multiplexed set of sequences of elements,
reset the OUT register,
perform a parallel MAX( ) operation between a subsequent sequence of elements and an output of the OUT register and store a resulting vector in the OUT register in response to receiving the subsequent sequence of elements,
perform MAX( ) operations across elements within the OUT register, and
produce a scalar value representing a maximum value across the corresponding portion of all arriving vectors associated with a corresponding one of the plurality of MAX compute circuits;
wherein each MAX compute circuit comprises:
an input bus;
an output bus;
a K-wide FMAX( ) comparator, a first set of K-wide inputs of the K-wide FMAX( ) comparator coupled to a read port of the memory and a second set of K-wide inputs of the K-wide FMAX( ) comparator coupled to the input bus, and a set of K-wide outputs of the K-wide FMAX( ) comparator coupled to a write port of the memory; and
a tree of FMAX( ) comparators, the tree comprising an input and an output, the input of the tree coupled to the set of K-wide outputs of the K-wide FMAX( ) comparator and the output of the tree coupled to the output bus, wherein the memory is configured to store N/K elements of an N-element vector in a corresponding row of the memory.
12 . The system of claim 11 , each MAX compute circuit further comprising an OUT register, an input of the OUT register coupled to the set of K-wide outputs of the K-wide FMAX( ) comparator and an output of the OUT register coupled to the write port of the memory.
13 . The system of claim 12 , wherein a controller is configured to initialize the OUT register, for an initial comparison operation, to a scalar value representing a largest-negative value capable of being stored in the OUT register.
14 . The system of claim 11 , each MAX compute circuit further comprising an OUT register, an input of the OUT register coupled to the output of the tree and an output of the OUT register coupled to the output bus.