IP Library › Granted Patent US 12,229,000
Granted Patent B2
US 12,229,000 · App. 18/207,525 · Granted Feb 18, 2025

Managing error-handling flows in memory devices

Inventors: Kishore Kumar Muchherla (San Jose, CA); Shane Nowell (Boise, ID); Mustafa N. Kaynak (San Diego, CA); Sampath K. Ratnam (San Jose, CA); Peter Feeley (Boise, ID); Sivagnanam Parthasarathy (Carlsbad, CA); Devin M. Batutis (San Jose, CA); Xiangang Luo (Fremont, CA)
Assignee: Micron Technology, Inc.
G06F11/0793G06F11/0727G06F11/0751
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Quick Facts
Patent No.
US 12,229,000
App. No.
18/207,525
Granted
Feb 18, 2025
Kind
B2
Abstract

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

Claims (43)

1. A system comprising:

a memory device; and

a processing device, operatively coupled to the memory device, to perform operations comprising:

detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is assigned to a voltage offset bin which defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations;

determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and

performing the error-handling operation to recover the data.

2. The system of claim 1 , wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin.

3. The system of claim 1 , wherein the operations further comprise:

maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

4. The system of claim 1 , wherein the operations further comprise:

adjusting an order of a set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations.

5. The system of claim 4 , wherein the operations further comprise:

in response to a current error-handling operation of the set of error-handling operations in the adjusted order recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the current error-handling operation.

6. The system of claim 4 , wherein the predetermined position is set during at least one of programming or calibration of the memory device.

7. The system of claim 4 , wherein the operations further comprise:

performing one or more error-handling operations of the set of error handling operations to recover the data in the adjusted order until data associated to the read error is recovered.

8. A method, comprising:

detecting a read error with respect to data residing in a first block of a memory device, wherein the first block is assigned to with a voltage offset bin which defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations;

determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and

performing the error-handling operation to recover the data.

9. The method of claim 8 , wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin.

10. The method of claim 8 , further comprising:

maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

11. The method of claim 8 , further comprising:

adjusting an order of a set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations.

12. The method of claim 11 , further comprising:

in response to a current error-handling operation of the set of error-handling operations in the adjusted order recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the current error-handling operation.

13. The method of claim 11 , wherein the predetermined position is set during at least one of programming or calibration of the memory device.

14. The method of claim 11 , further comprising:

performing one or more error-handling operations of the set of error handling operations to recover the data in the adjusted order until data associated to the read error is recovered.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operatively coupled to a memory, performs operations comprising:

detecting a read error with respect to data residing in a first block of a memory device, wherein the first block is assigned to with a voltage offset bin which defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations;

determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and

performing the error-handling operation to recover the data.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin.

17. The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise:

maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

18. The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise:

adjusting an order of a set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations.

19. The non-transitory computer-readable storage medium of claim 18 , wherein the operations further comprise:

in response to a current error-handling operation of the set of error-handling operations in the adjusted order recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the current error-handling operation.

20. The non-transitory computer-readable storage medium of claim 18 , wherein the operations further comprise:

performing one or more error-handling operations of the set of error handling operations to recover the data in the adjusted order until data associated to the read error is recovered.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2023
From: MUCHHERLA, KISHORE KUMAR; NOWELL, SHANE; KAYNAK, MUSTAFA N.; RATNAM, SAMPATH K.; FEELEY, PETER; PARTHASARATHY, SIVAGNANAM; BATUTIS, DEVIN M.; LUO, XIANGANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 063908/0979 →
Continuity (2)
Continuation 17216901 · Mar 30, 2021
Related Publication 20230325273A1 · Oct 12, 2023
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