IP Library Granted Patent US 12,469,680
Granted Patent B2
US 12,469,680 · App. 18/207,526 · Granted Nov 11, 2025

Radio-frequency (RF) matching network for fast impedance tuning

Inventors: Yue Guo (Redwood City, CA); A N M Wasekul Azad (Santa Clara, CA); Kartik Ramaswamy (San Jose, CA); Nicolas J. Bright (Arlington, WA); Yang Yang (San Diego, CA)
Assignee: Applied Materials, Inc.
H01J37/32183H01J37/32128
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,469,680
App. No.
18/207,526
Granted
Nov 11, 2025
Kind
B2
Abstract

Some embodiments are directed to a tuning circuit. The tuning circuit generally includes: a first impedance coupled between a first terminal and a second terminal of the tuning circuit, wherein the first terminal is coupled to a generator and the second terminal is coupled to a load; a second impedance coupled between the first impedance of the tuning circuit and a reference potential node; and a signal path coupled to the first impedance or the second impedance, the signal path comprising an inductive element and a first switch coupled to the inductive element, wherein a control input of the first switch is coupled to a control input of the tuning circuit configured to receive a control signal associated with a pulsed voltage (PV) waveform.

Claims (39)

1 . A tuning circuit, comprising:

a first impedance circuit coupled between a first terminal and a second terminal of the tuning circuit, wherein the first terminal is coupled to a generator and the second terminal is coupled to a load, the first impedance circuit being on a series path between the first terminal and the second terminal;

a second impedance circuit coupled between the first impedance circuit and a reference potential node; and

a signal path coupled to the first impedance circuit or the second impedance circuit, the signal path comprising an inductive element and a first switch coupled in parallel with the inductive element to form a parallel circuit, the parallel circuit being between the series path and the reference potential node, wherein a control input of the first switch is coupled to a control input of the tuning circuit configured to receive a control signal associated with a pulsed voltage (PV) waveform.

2 . The tuning circuit of claim 1 , wherein the parallel circuit further comprises a capacitive element coupled in series with the first switch.

3 . The tuning circuit of claim 1 , wherein the signal path including the parallel circuit is coupled in parallel with the first impedance circuit or the second impedance circuit.

4 . The tuning circuit of claim 1 , wherein the signal path further comprises a capacitive element coupled to the parallel circuit.

5 . The tuning circuit of claim 4 , wherein the signal path further comprises a second switch coupled between the capacitive element and the parallel circuit.

6 . The tuning circuit of claim 1 , wherein the signal path further comprises a second switch coupled in parallel with the second impedance circuit, the second switch being between the parallel circuit and the first terminal.

7 . The tuning circuit of claim 1 , wherein the signal path is in parallel with the first impedance circuit or the second impedance circuit, the first switch being in series with the inductive element.

8 . The tuning circuit of claim 7 , wherein the signal path comprises at least one capacitive element in series with the inductive element.

9 . A plasma processing system having the tuning circuit of claim 1 , the plasma processing system further including a controller having an output coupled to the control input of the tuning circuit, wherein the controller is configured to:

generate the control signal based on the PV waveform; and

provide the control signal to the control input of the tuning circuit.

10 . The plasma processing system of claim 9 , further comprising a PV waveform generator configured to deliver the PV waveform to an electrode disposed within a plasma chamber of the plasma processing system.

11 . The tuning circuit of claim 1 , wherein the control signal is configured to control the first switch based on stage transitions associated with the PV waveform.

12 . The tuning circuit of claim 1 , wherein the control signal is configured to control the first switch based on a processing chamber being in a sheath collapse stage or an ion current stage.

13 . A match circuit, comprising:

a tuning circuit including:

a first impedance circuit coupled between a first terminal and a second terminal of the tuning circuit, wherein the first terminal is coupled to a generator and the second terminal is coupled to a load;

a second impedance circuit coupled between the first impedance circuit and a reference potential node; and

a signal path coupled to the first impedance circuit or the second impedance, the signal path comprising an inductive element and a first switch coupled to the inductive element, wherein a control input of the first switch is coupled to a control input of the tuning circuit configured to receive a control signal associated with a pulsed voltage (PV) waveform; and

a bias circuit; and

a filter coupled between the control input of the tuning circuit and an output of the bias circuit.

14 . A method of processing a substrate in a plasma processing system, comprising:

generating a control signal based on a pulsed voltage (PV) waveform provided to an electrode of a processing chamber; and

providing the control signal to a control input for a tuning circuit, the tuning circuit further comprises:

a first impedance circuit coupled between a first terminal and a second terminal of the tuning circuit, wherein the first terminal is coupled to a generator and the second terminal is coupled to the processing chamber, the first impedance circuit being on a series path between the first terminal and the second terminal;

a second impedance circuit coupled between the first impedance circuit and a reference potential node; and

a signal path coupled to the first impedance circuit or the second impedance circuit, the signal path comprising an inductive element and a first switch coupled in parallel with the inductive element to form a parallel circuit, the parallel circuit being between the series path and the reference potential node, wherein a control input of the first switch is coupled to the control input of the tuning circuit.

15 . The method of claim 14 , further comprising controlling, via the control signal, the first switch based on stage transitions associated with the PV waveform.

16 . The method of claim 14 , further comprising controlling, via the control signal, the first switch based on the processing chamber being in a sheath collapse stage or an ion current stage.

17 . An apparatus for processing a substrate in a plasma processing system, comprising:

a pulsed voltage (PV) waveform generator configured to generate a PV waveform provided to an electrode of a processing chamber;

a tuning circuit including:

a first impedance circuit coupled between a first terminal and a second terminal of the tuning circuit, the first impedance circuit being on a series path between the first terminal and the second terminal;

a second impedance circuit coupled between the first terminal of the tuning circuit and a reference potential node; and

a signal path coupled to the first impedance circuit or the second impedance circuit, the signal path comprising an inductive element and a first switch coupled in parallel with the inductive element to form a parallel circuit, the parallel circuit being between the series path and the reference potential node, wherein a control input of the first switch is coupled to a control input of the tuning circuit; and

a controller configured to provide a control signal to the control input of the tuning circuit based on the PV waveform.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2024
From: GUO, YUE; AZAD, A N M WASEKUL; RAMASWAMY, KARTIK; BRIGHT, NICOLAS J.; YANG, YANG
To: APPLIED MATERIALS, INC.
Reel/Frame 066840/0915 →
Continuity (1)
Related Publication 20240412947A1 · Dec 12, 2024
References Cited (12)
US 10790784B2 · Jurkov · 2020 [cited by examiner]
US 12165844B2 · Marakhtanov · 2024 [cited by examiner]
US 20070221331A1 · Lee · 2007 [cited by applicant]
US 20100243606A1 · Koshimizu et al. · 2010 [cited by applicant]
US 20140361690A1 · Yamada et al. · 2014 [cited by applicant]
US 20190318919A1 · Lyndaker · 2019 [cited by examiner]
US 20200144032A1 · Ulrich · 2020 [cited by examiner]
US 20200185195A1 · Haga · 2020 [cited by examiner]
US 20200381214A1 · Leray et al. · 2020 [cited by applicant]
US 20220076923A1 · Carroll · 2022 [cited by examiner]
KR 20200069245A · 2020 [cited by applicant]
International Search Report and Written Opinion for International Application No. PCT/US2024/023851 dated Jul. 26, 2024. [cited by applicant]