IP Library Patent Application 18207918
Patent Application
App. No. 18/207,918

SYSTEMS, APPARATUSES, AND METHODS FOR NANOWIRES FOR SEMICONDCUTOR PACKAGES

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Quick Facts
Patent No.
US None
App. No.
18/207,918
Abstract

Systems, apparatuses, and method for nanowires for semiconductor packages are provided herein. The semiconductor package may include die attached to a substrate. A lid may also be attached to the substrate. The die includes die nanowires and the lid includes lid nanowires. The nanowires may be formed over the entirety of the die or in a pattern. The lid may have a corresponding or symmetrical coverage or pattern. In the semiconductor package, the die nanowires and the lid nanowires are coupled to, among other things, provide improved heat dissipation.

Claims (28)

1 . A semiconductor package comprising:

a substrate;

a die including a first side of the die and a second side of the die, wherein the first side of the die includes a plurality of formations of die nanowires, wherein the second side of the die is coupled to the substrate;

a lid including a first side of the lid facing the die, wherein the first side of the lid includes a plurality of formations of lid nanowires; and

wherein at least one formation of die nanowires is coupled to at least one formation of lid nanowires.

2 . The semiconductor package of claim 1 , wherein the lid is comprised of a lid top portion and a plurality of lid side portions, and the lid top portion is coupled to the lid side portions with a glue.

3 . The semiconductor package of claim 1 , wherein the least one of the plurality of formations of die nanowires is coupled to at least one of the plurality of formations of lid nanowires, and wherein the coupling is aligned with a shared a common axis.

4 . The semiconductor package of claim 1 , wherein at least one of the plurality of formations of die nanowires is coupled to at least one of the plurality of formations of lid nanowires, and wherein the coupling is misaligned with the at least one of the plurality of formations of die nanowires having a different axis than the at least one of the plurality of formations of lid nanowires.

5 . The semiconductor package of claim 1 , wherein the plurality of formations of lid nanowires covers a first portion of the first side of the lid that is not an entirety of the of the first side of the lid.

6 . The semiconductor package of claim 1 , wherein the plurality of formations of die nanowires covers a first portion of the first side of the die that is not an entirety of the first side of the die.

7 . The semiconductor package of claim 6 , wherein the first portion of the first side of the die covered by the plurality of formations of die nanowires includes coverage of at least one die hot spot.

8 . The semiconductor package of claim 1 , wherein the plurality of formations of die nanowires are in a first pattern, wherein the plurality of formation of lid nanowires are in a second pattern, and wherein the first pattern and second pattern are complimentary patterns.

9 . The semiconductor package of claim 1 , wherein the first side of the lid covers one or more circuitries in addition to the die.

10 . The semiconductor package of claim 9 , wherein the plurality of formations of lid nanowires are only on a first portion of the lid associated with the die.

11 . A method of manufacturing a semiconductor package comprising:

growing a plurality of formations of die nanowires on a first side of a die;

growing a plurality of formations of lid nanowires on a first side of a lid;

attaching the die to a substrate;

attaching the lid to the substrate including coupling the plurality of formations of die nanowires to the plurality of formations of the lid nanowires.

12 . A method of manufacturing a semiconductor package of claim 11 , wherein the lid is comprised of a lid top portion and a plurality of lid side portions, and the lid top portion is coupled to the lid side portions with a glue.

13 . A method of manufacturing a semiconductor package of claim 11 , wherein at least one formation of die nanowires is coupled to at least one formation of lid nanowires, and wherein the coupling is aligned with a shared a common axis.

14 . A method of manufacturing a semiconductor package of claim 11 , wherein at least one formation of die nanowires is coupled to at least one formation of lid nanowires is misaligned with the at least one formation of die nanowires having an axis that is different from the at least one formation of lid nanowires.

15 . A method of manufacturing a semiconductor package of claim 11 , wherein the plurality of formations of lid nanowires cover a first portion of the first side of the lid that is not an entirety of the first side of the lid.

16 . A method of manufacturing a semiconductor package of claim 11 , wherein the plurality of formations of die nanowires covers a first portion of the first side of the die that is not the entirety of the first side of the die.

17 . A method of manufacturing a semiconductor package of claim 16 , wherein the first portion of the first side of the die covered by the plurality of formations of die nanowires includes coverage of at least one die hot spot.

18 . A method of manufacturing a semiconductor package of claim 11 , wherein the plurality of formations of die nanowires are in a first pattern, wherein the plurality of formation of lid nanowires are in a second pattern, and wherein the first pattern and the second pattern are complimentary patterns.

19 . A method of manufacturing a semiconductor package of claim 11 , wherein the first side of the lid covers one or more circuitries in addition to the die.

20 . A method of manufacturing a semiconductor package of claim 19 , wherein the plurality of formations of lid nanowires are only on a first portion of the lid associated with the die.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2024
From: STMICROELECTRONICS (ALPS) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068449/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2024
From: STMICROELECTRONICS (GRENOBLE 2) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068449/0739 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2023
From: SCHWARTZ, LAURENT
To: STMICROELECTRONICS (ALPS) SAS
Reel/Frame 063909/0639 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2023
From: COFFY, ROMAIN; FOURNEAUD, LUDOVIC
To: STMICROELECTRONICS (GRENOBLE 2) SAS
Reel/Frame 063909/0979 →