Digital-domain-integrated, voltage-to-frequency temperature sensor

1 . An integrated circuit comprising:

a bandgap reference circuit configured to generate, from a digital chip supply voltage, a reference voltage and a proportional-to-absolute temperature (PTAT) voltage; and

a voltage-to-frequency (VTF) readout circuit to receive the reference voltage and the PTAT voltage as inputs, wherein the VTF readout circuit comprises:

sets of switched capacitors that operate as a voltage divider, wherein one or more capacitors of the sets of switched capacitors are selectively charged by the PTAT voltage via first switches of the sets of switched capacitors to generate a feedback voltage, and wherein the one or more capacitors being selectively charged operate as a frequency-to-current converter;

a voltage-controlled oscillator (VCO) driven by a difference between the feedback voltage and the reference voltage and to generate a VCO clock; and

a clock generator to generate a feedback clock based on the VCO clock, wherein the first switches of the sets of switched capacitors are controlled by the feedback clock.

2 . The integrated circuit of claim 1 , further comprising a digital counter coupled to the clock generator, the digital counter to generate a digital output based on a number of cycles of a reference clock that fit into a cycle of the feedback clock, the digital output being linearly proportional to a temperature on which the PTAT voltage is based.

3 . The integrated circuit of claim 1 , wherein the VTF readout circuit is implemented as a closed loop and further comprises an integrator coupled to the sets of switched capacitors, the integrator comprising:

an operational amplifier that receives the reference voltage at a negative terminal and the feedback voltage at a positive terminal; and

an integrator capacitor coupled between the negative terminal and an output of the operational amplifier.

4 . The integrated circuit of claim 3 , wherein the VTF readout circuit further comprises a loop filter coupled between the integrator and the VCO, the loop filter comprising an in-line resistor and a filter capacitor coupled between the in-line resistor and ground.

5 . The integrated circuit of claim 1 , wherein the VCO comprises:

an input transistor to receive a filtered feedback voltage;

a current-starved ring oscillator;

a current mirror coupled between the input transistor and the current-starved ring oscillator, the current mirror to level-shift up the filtered feedback voltage; and

a rail-to-rail amplifier coupled to an output of the current-starved ring oscillator, the rail-to-rail amplifier to level-shift up the output to generate the VCO clock.

6 . The integrated circuit of claim 5 , wherein the current-starved ring oscillator comprises a plurality of inverter stages, each comprising a variable-controlled capacitor, that are configurable to control a gain of the VCO.

7 . The integrated circuit of claim 1 , wherein the VTF readout circuit further comprises a clock divider coupled to an output of the VCO, the clock divider to divide the VCO clock into a divided clock, wherein the clock generator is a first clock generator configured to convert the divided clock into two pairs of differential clock signals that are also non-overlapping, and wherein capacitors of a first bank of switched capacitors receive the PTAT voltage and are selectively controlled by the two pairs of differential clock signals.

8 . The integrated circuit of claim 7 , wherein the VTF readout circuit further comprises a second clock generator configured to convert a reference clock into a pair of clock signals that are also non-overlapping, wherein switches of a second bank of switched capacitors of the sets of switched capacitors are controlled by the pair of clock signals.

9 . The integrated circuit of claim 1 , wherein the first switches are part of a first bank of switched capacitors, and wherein the bandgap reference circuit comprises:

a plurality of rail transistors configured to operate in a sub-threshold region;

an operational transconductance amplifier (OTA) to control the plurality of rail transistors and coupled within a current mirror formed by the plurality of rail transistors; and

a chopper circuit coupled between terminals of the OTA and gates of the plurality of rail transistors, the chopper circuit controlled by a reference clock also used to control a second bank of switched capacitors of the sets of switched capacitors.

10 . A digital-domain-based thermal sensor comprising:

a filter to filter a digital chip supply voltage into a filtered digital supply voltage;

a bandgap reference circuit configured to generate, from the filtered digital supply voltage, a reference voltage and a proportional-to-absolute temperature (PTAT) voltage; and

a closed-loop readout circuit coupled to the bandgap reference circuit and comprising:

sets of switched capacitors that operate as a voltage divider, wherein capacitors of the sets of switched capacitors are selectively charged by the PTAT voltage and generate a feedback voltage;

a voltage-controlled oscillator (VCO) driven by a difference between the feedback voltage and the reference voltage and to generate a VCO clock; and

a clock generator to generate a feedback clock based on the VCO clock, wherein first switches of the sets of switched capacitors are controlled by the feedback clock; and

a digital counter coupled to the clock generator, the digital counter to generate a digital output based on a number of cycles of a reference clock that fit into a cycle of the feedback clock.

11 . The digital-domain-based thermal sensor of claim 10 , wherein the closed-loop readout circuit further comprises an integrator coupled to the sets of switched capacitors, the integrator comprising:

an operational amplifier that receives the reference voltage at a negative terminal and the feedback voltage at a positive terminal; and

an integrator capacitor coupled between the negative terminal and an output of the operational amplifier.

12 . The digital-domain-based thermal sensor of claim 11 , wherein the closed-loop readout circuit further comprises a loop filter coupled between the integrator and the VCO, the loop filter comprising an in-line resistor and a filter capacitor coupled between the in-line resistor and ground.

13 . The digital-domain-based thermal sensor of claim 10 , wherein the VCO comprises:

an input transistor to receive a filtered feedback voltage;

a current-starved ring oscillator;

a current mirror coupled between the input transistor and the current-starved ring oscillator, the current mirror to level-shift up the filtered feedback voltage; and

a rail-to-rail amplifier coupled to an output of the current-starved ring oscillator, the rail-to-rail amplifier to level-shift up the output to generate the VCO clock.

14 . The digital-domain-based thermal sensor of claim 13 , wherein the current-starved ring oscillator comprises a plurality of inverter stages, each comprising a variable-controlled capacitor, that are configurable to control a gain of the VCO.

15 . The digital-domain-based thermal sensor of claim 10 , wherein the closed-loop readout circuit further comprises a clock divider coupled to an output of the VCO, the clock divider to divide the VCO clock into a divided clock, wherein the clock generator is a first clock generator configured to convert the divided clock into two pairs of differential clock signals that are also non-overlapping, and wherein capacitors of a first bank of switched capacitors receive the PTAT voltage and are selectively controlled by the two pairs of differential clock signals.

16 . The digital-domain-based thermal sensor of claim 15 , wherein the closed-loop readout circuit further comprises a second clock generator configured to convert a reference clock into a pair of clock signals that are also non-overlapping, wherein a second bank of switched capacitors of the sets of switched capacitors is controlled by the pair of clock signals.

17 . The digital-domain-based thermal sensor of claim 10 , wherein the first switches are part of a first bank of switched capacitors, and wherein the bandgap reference circuit comprises:

a plurality of rail transistors configured to operate in a sub-threshold region;

an operational transconductance amplifier (OTA) to control the plurality of rail transistors and coupled within a current mirror formed by the plurality of rail transistors; and

a chopper circuit coupled between terminals of the OTA and gates of the plurality of rail transistors, the chopper circuit controlled by a reference clock also used to control a second bank of switched capacitors of the sets of switched capacitors.

18 . A network communication switch comprising:

an integrated circuit chip comprising a digital chip supply voltage and configured to process network packets over one or more ports, wherein the integrated circuit chip comprises:

a filter to filter the digital chip supply voltage into a filtered digital supply voltage;

a bandgap reference circuit configured to generate, from the filtered digital supply voltage, a reference voltage and a proportional-to-absolute temperature (PTAT) voltage; and

a closed-loop readout circuit coupled to the bandgap reference circuit and comprising:

sets of switched capacitors that operate as a voltage divider, wherein one or more capacitors of the sets of switched capacitors are selectively charged by the PTAT voltage via first switches of the sets of switched capacitors to generate a feedback voltage, and wherein the one or more capacitors being selectively charged operate as a frequency-to-current converter;

a voltage-controlled oscillator (VCO) driven by a difference between the feedback voltage and the reference voltage and to generate a VCO clock; and

a clock generator to generate a feedback clock based on the VCO clock, wherein switches of a first bank of switched capacitors of the sets of switched capacitors are controlled by the feedback clock.

19 . The network communication switch of claim 18 , further comprising a digital counter coupled to the clock generator, the digital counter to generate a digital output based on a number of cycles of a reference clock that fit into a cycle of the feedback clock, the digital output being linearly proportional to a temperature on which the PTAT voltage is based.

20 . The network communication switch of claim 18 , wherein the closed-loop readout circuit further comprises a clock divider coupled to an output of the VCO, the clock divider to divide the VCO clock into a divided clock, wherein the clock generator is a first clock generator configured to convert the divided clock into two pairs of differential clock signals that are also non-overlapping, and wherein capacitors of the first bank of switched capacitors receive the PTAT voltage and are selectively controlled by the two pairs of differential clock signals.

21 . The network communication switch of claim 20 , wherein the closed-loop readout circuit further comprises a second clock generator configured to convert a reference clock into a pair of clock signals that are also non-overlapping, wherein a second bank of switched capacitors of the sets of switched capacitors is controlled by the pair of clock signals.