Method for programming an FPGA
A method for programming an FPGA, wherein a library with elementary operations and a respective latency table for each of the elementary operations of the library are provided. a data path is defined. The latencies are recorded for a multiplicity of clock rates that are different from one another and these latencies are added for every clock rate so that a total latency for the data path results for this multiplicity of different clock rates. The ratio between the lowest total latency and the total latency at a respective clock rate is determined. A utilization of the FPGA for each clock rate is identified. The ratio between the lowest utilization of the FPGA and the utilization of the FPGA at a respective clock rate is determined. A quality factor for each clock rate while taking into account the total latency and the utilization of the FPGA is determined.
1. A method for programming an FPGA, wherein a library with elementary operations that are executable on the FPGA and a respective latency table for each of the elementary operations of the library are provided, wherein each latency table specifies, for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the respective operation, the latency of the respective operation during execution on the FPGA as a function of the input bit width of the respective operation and the clock rate of the FPGA, the method comprising:
defining a data path that specifies a sequential execution on the FPGA of at least two elementary operations of the library;
recording the latencies given by the respective input bit width of the respective elementary operations of the data path for a multiplicity of clock rates that are different from one another in the latency tables;
adding the recorded latencies for every clock rate so that a total latency for the data path results in each case for this multiplicity of different clock rates;
determining a lowest total latency;
determining, for all clock rates, a ratio between a lowest total latency and a total latency at a respective clock rate;
identifying a utilization of the FPGA for each clock rate;
determining a lowest utilization of the FPGA;
determining, for all clock rates, a ratio between the lowest utilization of the FPGA and the utilization of the FPGA at a respective clock rate; and
determining a quality factor for each clock rate while taking into account the total latency and the utilization of the FPGA,
wherein the utilization of the FPGA at a specific clock rate includes the resource demand and/or the power demand on the FPGA at the clock rate in question,
wherein the resource demand or the power demand on the FPGA is identified at a specific clock rate with the aid of previously provided resource demand tables or power demand tables, and
wherein the resource demand tables or the power demand tables specify the resource demand or the power demand of a specific operation during execution on the FPGA as a function of the input bit width of the specific operation and the clock rate of the FPGA for a multiplicity of clock rates of the FPGA and for a multiplicity of input bit widths of the specific operation.
2. The method according to claim 1 , wherein the determination of the quality factor for each clock rate is carried out via a mathematical optimization method so that the quality factor with regard to the utilization of the FPGA and the total latency reflects a compromise between minimum utilization and minimum total latency.
3. The method according to claim 1 , wherein the determination of the quality factor for each clock rate is carried out through addition of the ratio between the lowest total latency and the total latency at the respective clock rate and the ratio between the lowest utilization of the FPGA and the utilization of the FPGA at the respective clock rate, and the ratio between the lowest total latency and the total latency at each clock rate is weighted with a latency weighting factor, and wherein the ratio between the lowest utilization of the FPGA and the utilization of the FPGA at each clock rate is weighted with a utilization weighting factor.
4. The method according to claim 3 , wherein the latency weighting factor is the same for all clock rates.
5. The method according to claim 3 , wherein the utilization weighting factor is the same for all clock rates.
6. The method according to claim 1 , wherein the resource demand tables or the power demand tables have been created in advance through measurements on an FPGA of the same type.
7. The method according to claim 1 , wherein the latency tables have been created in advance through measurements on an FPGA of the same type.
8. The method according to claim 1 , wherein the clock rates at which the utilization of the FPGA is above a predetermined utilization limit are rejected prior to the step of determining the ratio between the lowest utilization of the FPGA and the utilization of the FPGA at a specific clock rate.
9. The method according to claim 1 , further comprising: choosing the clock rate that is associated with the highest quality factor.
10. The method according to claim 1 , wherein the elementary operations of the library cannot be further subdivided.
11. The method according to claim 1 , wherein the elementary operations of the library are elementary blocks from a block library of a programming environment designed for creating program logic in the form of a flow diagram constructed from elementary blocks.
12. A non-transitory, computer-readable storage medium with instructions stored thereon that implement the method according to claim 1 when they are executed on a processor.