Method for effectively increasing a memory on an FPGA
In an FPGA, a memory of the FPGA is to be effectively increased. This is achieved by a computer-implemented method for implementing a model-adaptive cache memory having a model state-dependent memory look-ahead on the FPGA.
1. A computer-implemented method for implementing a model-adaptive cache memory having a model state-dependent memory look-ahead on an FPGA for effectively increasing a first memory of the FPGA, the method comprising:
setting up an application on the FPGA, the application comprising a state interface, so that a current state of the application is read out from an outside at runtime;
specifying, in the application, data which require a fast access at runtime, the data being marked as caching data, the caching data being preloaded at runtime;
setting up a memory interface for reading out the first memory by the application, the bit width of the memory interface being model-adaptively specified such that the application is able to read out within one clock pulse all data stored in the first memory or a data structure stored in the first memory, which comprises a plurality of data entries;
storing the specified caching data at least partially in a second memory during the setup of the application on the FPGA;
storing a routine for managing the cache memory on the FPGA, the routine setting up the first memory as a cache memory for the specified data, the routine comprising a state input, which is linked with the state interface of the application;
storing an overview on the FPGA, in which possible states of the application are assigned to data from the second memory which will probably be accessed by the application in a subsequent state, the routine continuously consulting the overview at runtime and transferring caching data which will probably be accessed by the application in a subsequent state from the second memory to the first memory; and
accessing the caching data shifted to the first memory by the application, the access taking place via the memory interface.
2. The computer-implemented method according to claim 1 , wherein the step of storing an overview on the FPGA comprises:
storing at least two probability tables for each possible current state on the FPGA, a first probability P SegmentUsage (s) indicating the probability of the state accessing certain data, and a second probability indicating the probability P StateTransition (s) of certain states following the current state; and
calculating a segment probability P Segment (s) from the two probability tables for the current state as to which data will probably be accessed by the application in the subsequent state, the data having the highest probability being anticipatorily loaded to the first memory of the FPGA.
3. The computer-implemented method according to claim 2 , wherein, in the step of calculating a segment probability P Segment (s) from the two probability tables for the current state, the data which will be accessed by the application in the subsequent state are calculated using the following formula:
P
Segment
(
s
)
=
∑
S
Subsequent
=
1
n
P
StateTransition
(
s
,
s
Subsequent
)
·
P
SegmentUsage
(
s
Subsequent
)
4. The computer-implemented method according to claim 3 , wherein, if the most probable blocks are present in the cache memory, the transfer from the second memory to the first memory is paused until the segment probabilities P Segment (s) have changed.
5. The computer-implemented method according to claim 3 , wherein the segment probabilities P Segment (s) are calculated offline for each state or are calculated online in the FPGA.
6. The computer-implemented method according to claim 1 , wherein the first memory is a block RAM memory of the FPGA.
7. The computer-implemented method according to claim 1 , wherein, in addition to the model-adaptive bit width, a model-adaptive memory depth of the application is also specified.
8. The computer-implemented method according to claim 1 , wherein the state is predefined by a state vector or a finite state machine.
9. The computer-implemented method according to claim 1 , wherein the routine in the cache overwrites data for which a low probability is stored in the current state.
10. The computer-implemented method according to claim 1 , wherein the overview is predefined and is loaded to the FPGA together with the application in the form of a lookup table.
11. The computer-implemented method according to claim 1 , wherein the overview is created manually based on an analysis of the model or is generated in a self-learning manner based on a simulation of the application.
12. The computer-implemented method according to claim 1 , wherein the overview is self-learning and is automatically generated at runtime by logging the program run.
13. The computer-implemented method according to claim 1 , wherein the subsequent state is temporally removed from the current state in each case by no more than N state changes of the application, N being a low natural number measured by the total number of state changes taking place at the runtime of the application, and wherein N<100, N<10, or N=1.
14. The computer-implemented method according to claim 1 , wherein the method implements a model-adaptive cache memory having a model state-dependent memory look-ahead on an FPGA for increasing a first memory of the FPGA in rapid control prototyping applications and hardware in the loop applications.
15. A non-transitory computer-readable media comprising commands, which, when executed by a computer carries out a method for implementing a model-adaptive cache memory having a model state-dependent memory look-ahead on an FPGA for effectively increasing a first memory of the FPGA, the method comprising:
setting up an application on the FPGA the application comprising a state interface, so that a current state of the application is read out from an outside at runtime;
specifying, in the appiication, data which require a fast access at runtime, the data being marked as caching data, the caching data being preloaded at runtime;
setting up a memory interface for reading out the first memory by the application, the bit width of the memory interface being model-adaptively specified such that the application is able to read out within one clock pulse all data stored in the first memory or a data structure stored in the first memory, which comprises a plurality of data entries;
storing the specified caching data at least partially in a second memory durino the setup of the application on the FPGA;
storing a routine for managing the cache memory on the FPGA, the routine setting up the first memory as a cache memory for the specified data, the routine comprising a state input, which is linked with the state interface of the application;
storing an overview on the FPGA, in which possible states of the application are assigned to data from the second memory which will probably be accessed by the application in a subsequent state, the routine continuously consulting the overview at runtime and transferring caching data which will probably be accessed by the application in a subsequent state from the second memory to the first memory; and
accessing the caching data shifted to the first memory by the application, the access taking place via the memory interface.