Cache bypass
Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.
1. An apparatus, comprising:
a memory device; and
a memory controller, coupled to the memory device, comprising a cache, and configured to cause performance of a cache look-up operation associated with the cache, wherein the cache includes a cache sequence controller configured to:
determine a quantity of a given type of result of cache look-up operations associated with the cache;
determine the quantity satisfies a bypass threshold; and
cause performance of a bypass memory operation, substantially contemporaneously with the performance of the cache look-up operation, that bypasses the cache and accesses the memory device;
wherein performance of the cache look-up operation results in a cache miss; and
wherein, responsive to a determination that the cache is a clean cache, the cache sequence controller is configured to cache-in any data associated with the performance of the bypass memory operation in the cache.
2. The apparatus of claim 1 , wherein performance of the cache look-up operation results in a cache hit, and wherein the cache sequence controller is further to discard any data associated with the bypass memory operation.
3. The apparatus of claim 1 , wherein, responsive to a determination that the cache is a dirty cache:
the cache sequence controller is further to cache-in data associated with the performance of the bypass memory operation in the cache; and
the memory controller is to cause performance of a cache write-back operation to write data from the cache to the memory device.
4. The apparatus of claim 1 , wherein the memory controller includes metric logic including counters to collect metrics, wherein the metrics include information corresponding to respective counts of the counters, and wherein the counters comprise a cache hit counter, write hit counter, or a combination thereof.
5. The apparatus of claim 1 , wherein the cache further comprises a cache memory and a cache controller.
6. The apparatus of claim 1 , wherein the cache look-up operations are consecutive look-up operations, and wherein the quantity of the given type of result is a quantity of cache misses or a quantity of cache hits resulting from the consecutive look-up operations.
7. A system, comprising:
a memory device; and
a memory controller coupled to the memory device and configured to perform cache look-up operations associated with a cache responsive to host read requests associated with the memory device, wherein the cache comprises:
a metric logic including counters, the metric logic configured to collect, within a threshold amount of time, metrics related to the cache look-up operations; and
a cache sequence controller to:
determine, based on the collected metrics, a quantity of a given type of result of the cache look-up operations associated with the cache;
determine the quantity of the given type of result satisfies a bypass threshold;
responsive to the determination that the quantity of the given type of result satisfies the bypass threshold:
perform a cache look-up operation to determine a cache hit or a cache miss corresponding to a host read request; and
in parallel with performance of the cache look-up operation, initiate a bypass read operation to read data corresponding to the host read request from the memory device.
8. The system of claim 7 , wherein the counters comprise:
a cache hit counter configured to increase when a cache hit is detected, and a cache miss counter configured to increase when a cache miss is detected.
9. The system of claim 7 , wherein the cache sequence controller is to cause performance of a plurality of bypass read operations until the quantity of the given type of result is less than or equal to the bypass threshold.
10. The system of claim 9 , further comprising an exit threshold that is less than the bypass threshold, and wherein the cache sequence controller is to cause performance of a plurality of bypass read operations until the quantity of the given type of result is less than or equal to the exit threshold.
11. The system of claim 7 , wherein the cache sequence controller is configured to:
track a cache metric corresponding to the cache; and
responsive to the cache metric meeting a particular criteria, enable a cache bypass function, wherein when the cache bypass function is enabled, the cache sequence controller is configured to:
perform the cache look-up operation to determine the cache hit or a cache miss corresponding to the host read request; and
in parallel with performance of the cache look-up operation, initiate a bypass read operation to read data corresponding to the host read request from the memory device.
12. The system of claim 7 , wherein the bypass threshold is variable, wherein the variable bypass threshold is determined based on a cache hit rate of cache-look operations associated with the cache.
13. The system of claim 12 , wherein:
the bypass threshold is decreased based on the cache hit rate being above a target hit rate; and
the bypass threshold is increased based on the cache hit rate being below a target hit rate.
14. A method, comprising:
receiving a read request at a controller coupled to a memory device;
performing cache look-up operations on a cache of a central controller portion;
collecting, over a threshold amount of time, metrics associated with performing the cache look-up operations;
determining, based on the collected metrics, a quantity of cache misses resulting from performance of a quantity of consecutive cache look-up operations associated with the cache;
determining the quantity of cache misses satisfies a bypass threshold; and
responsive to determining the quantity of cache misses satisfies the bypass threshold:
causing performance of a bypass read operation that bypasses the cache and accesses the memory device in response to a host access request; and
causing performance of a cache look-up operation associated with the cache in response to the host access request substantially contemporaneously with the performance of the bypass read operation.
15. The method of claim 14 , wherein the cache look-up operations comprise a plurality of consecutive cache look-up operations, and further comprising:
determining a quantity of consecutive cache misses resulting from performance of the plurality of consecutive cache look-up operations, and
determining the quantity of consecutive cache misses exceeds the bypass threshold.
16. The method of claim 14 , wherein data associated with the performance of the bypass read operation is selectively utilized based on a type of respective result of the cache look-up operations.
17. The method of claim 14 , wherein the threshold amount of time is variable based on a hit rate or a miss rate of the cache look-up operations.