Electronic device comprising substrate assembly including two types of transistors
A substrate assembly includes: a substrate; a first transistor disposed on the substrate, wherein the first transistor includes a first semiconductor layer and the first semiconductor layer is a silicon semiconductor layer; and a second transistor disposed on the substrate, wherein the second transistor includes a second semiconductor layer and a drain electrode electrically connected to the second semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer, wherein the first semiconductor layer of the first transistor is electrically insulated from the drain electrode of the second transistor.
1. A substrate assembly, comprising:
a substrate;
a first transistor disposed on the substrate, wherein the first transistor comprises a first semiconductor layer and a first drain electrode electrically connected to the first semiconductor layer, and the first semiconductor layer is a silicon semiconductor layer;
a second transistor disposed on the substrate, wherein the second transistor comprises a second semiconductor layer, a second source electrode and a second drain electrode electrically connected to the second semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer;
a first insulating layer disposed under the first semiconductor layer;
a second insulating layer disposed on the first semiconductor layer;
a first buffer layer disposed between the substrate and the first insulating layer;
a second buffer layer disposed between the substrate and the first buffer layer;
wherein a ratio of a thickness of the first insulating layer to a thickness of the second insulating layer is greater than or equal to 1.25 and less than or equal to 4;
wherein the first insulating layer comprises silicon oxide, the first buffer layer comprises silicon nitride, and the second buffer layer comprises silicon oxide;
wherein the first drain electrode is electrically connected to the second source electrode.
2. The substrate assembly of claim 1 , wherein the substrate comprises a peripheral region and an active region, and the peripheral region is adjacent to the active region.
3. The substrate assembly of claim 2 , wherein the first transistor is disposed on the peripheral region, and the second transistor is disposed on the active region.
4. The substrate assembly of claim 1 , wherein the second transistor further comprises a gate electrode disposed under the second semiconductor layer.
5. The substrate assembly of claim 1 , wherein the second drain electrode of the second transistor comprises a first layer, a second layer and a third layer, and the second layer is disposed between the first layer and the third layer.
6. The substrate assembly of claim 5 , wherein the first layer contacts the second semiconductor layer.
7. The substrate assembly of claim 5 , wherein a material of the first layer comprises Ti.
8. The substrate assembly of claim 5 , wherein a material of the second layer comprises Al.
9. The substrate assembly of claim 5 , wherein a material of the third layer comprises Ti.
10. The substrate assembly of claim 1 , wherein a thickness of the first insulating layer is greater than or equal to 200 nm and less than or equal to 500 nm.