IP Library › Granted Patent US 12,112,071
Granted Patent B2
US 12,112,071 · App. 18/217,063 · Granted Oct 8, 2024

Nonvolatile memory device supporting high-efficiency I/O interface

Inventors: Seonkyoo Lee (Hwaseong-si, KR); Jeongdon Ihm (Seongnam-si, KR); Chiweon Yoon (Seoul, KR); Byunghoon Jeong (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/0659G06F1/06G06F3/0613G06F3/0679G06F13/1668G11C16/0483G11C16/10G11C16/26
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Quick Facts
Patent No.
US 12,112,071
App. No.
18/217,063
Filed
Jun 30, 2023
Granted
Oct 8, 2024
Kind
B2
Art Unit
2827
USPC
711/103
Abstract

A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

Claims (46)

1. A nonvolatile memory device comprising:

a memory interface circuit configured to:

receive, from a memory controller via first signal lines, a first control signal and a second control signal during a first cycle period and a second cycle period from among time periods included in a predetermined number of cycle periods,

receive a write enable signal from the memory controller via a second signal line,

obtain a command from the first control signal and the second control signal received during remaining cycle periods of the time periods based on a toggle timing of the write enable signal, when the first control signal and the second control signal received during the first and the second cycle periods are in a first state, and

obtain an address from the first control signal and the second control signal received during the remaining cycle periods based on a toggle timing of the write enable signal, when the first control signal and the second control signal received during the first and the second cycle periods are in a second state.

2. The nonvolatile memory device of claim 1 , wherein the memory interface circuit is further configured to:

receive data signals from the memory controller via a third line, and

obtain write data from the data signals when the first control signal and the second control signal received during the first and the second cycle periods are in a third state.

3. The nonvolatile memory device of claim 1 , wherein the memory interface circuit is further configured to:

output data signals to the memory controller via a third line when the first control signal and the second control signal received during the first and the second cycle periods are in a fourth state.

4. The nonvolatile memory device of claim 1 , wherein the first state and the second state are different from each other.

5. The nonvolatile memory device of claim 1 , wherein, when the first control signal received during a first cycle period is in an enable state, the memory interface circuit obtains the command from the first control signal and the second control signal received during the remaining cycle periods based on the toggle timing of the write enable signal.

6. The nonvolatile memory device of claim 5 , wherein the second control signal received during a first cycle period is in a disable state.

7. The nonvolatile memory device of claim 1 , wherein, when the first control signal received during a first cycle period is in a disable state, the memory interface circuit obtains the address from the first control signal and the second control signal received during the remaining cycle periods based on the toggle timing of the write enable signal.

8. The nonvolatile memory device of claim 7 , wherein the second control signal received during a first cycle period is in a disable state.

9. The nonvolatile memory device of claim 1 , wherein the predetermined number of cycle periods are six cycle periods.

10. The nonvolatile memory device of claim 1 , wherein the first control signal is latched at first edge of the write enable signal during the first cycle period and the second control signal is latched at second edge of the write enable signal during the second cycle period.

11. A method of operating a memory interface circuit comprising:

receiving, from a memory controller via first signal lines, a first control signal and a second control signal during a first cycle period and a second cycle period from among time periods included in a predetermined number of cycle periods;

receiving a write enable signal from a memory controller via a second signal line;

obtaining a command from the first control signal and the second control signal received during remaining cycle periods of the time periods based on a toggle timing of the write enable signal, when the first control signal and the second control signal received during the first and the second cycle periods are in a first state; and

obtaining an address from the first control signal and the second control signal received during the remaining cycle periods based on a toggle timing of the write enable signal when the first control signal and the second control signal received during the first and the second cycle periods are in a second state.

12. The method of claim 11 , further comprising:

receiving data signals from the memory controller via a third line; and

obtaining write data from the data signals when the first control signal and the second control signal received during the first and the second cycle periods are in a third state.

13. The method of claim 11 , further comprising:

outputting data signals to the memory controller via a third line when the first control signal and the second control signal received during the first and the second cycle periods are in a fourth state.

14. The method of claim 11 , wherein first state and the second state are different from each other.

15. The method of claim 11 , wherein the predetermined number of cycle periods are six cycle periods.

16. The method of claim 10 , wherein the first control signal is latched at first edge of the write enable signal during the first cycle period and the second control signal is latched at second edge of the write enable signal during the second cycle period.

17. A memory system comprising:

a memory controller;

a memory cell array; and

a memory interface circuit configured to,

receive, from a memory controller via first signal lines, a first control signal and a second control signal during a first cycle period from among time periods included in a predetermined number of cycle periods from the memory controller via first signal lines,

receive, from the memory controller via the first signal line, a first control signal and a second control signal during a second cycle period from among the time periods,

receive a write enable signal from the memory controller via a second signal line,

obtain a command from the first control signal and the second control signal received during remaining cycle periods of the time periods based on a toggle timing of the write enable signal when the first control signal and the second control signal received during the first and the second cycle periods are in a first state, and

obtain an address from the first control signal and the second control signal received during the remaining cycle periods based on a toggle timing of the write enable signal when the first control signal and the second control signal received during the first and the second cycle periods are in a second state.

18. The memory system of claim 17 , the memory interface circuit further configured to,

receive data signals from the memory controller via a third line,

obtain write data from the data signals when the first control signal and the second control signal received during the first and the second cycle periods are in a third state.

19. The memory system of claim 17 , the memory interface circuit further configured to:

output data signals to the memory controller via a third line when the first control signal and the second control signal received during the first and the second cycle periods are in a fourth state.

20. The memory system of claim 17 , wherein the predetermined number of cycle periods are six cycle periods.

Priority Claims (1)
KR 10-2020-0086227 · Jul 13, 2020 · national
Continuity (3)
Continuation 17828176 · May 31, 2022
Continuation 17168620 · Feb 5, 2021
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