Granted Patent B2

US 12,517,172 · App. 18/217,292 · Granted Jan 6, 2026

Inventors: Nithin Gopinath (Bangalore, IN); Sai Aditya Nurani (Bengalaru, IN); Viswanathan Nagarajan (Bangalore, IN); Himanshu Varshney (Bangalore, IN); Mishab I (Manjeri, IN); Mujammil Patel (Mumbai, IN)

Assignee: TEXAS INSTRUMENTS INCORPORATED

G01R31/31703

Abstract

Claims (58)

1 . Programmable circuitry configured to:

determine a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage;

determine a first output voltage from the second ADC responsive to the first ADC and the second ADC both receiving the first input voltage;

determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and

determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

2 . The programmable circuitry of claim 1 , wherein:

the first input voltage is a sum of a first dither signal produced by the programmable circuitry and an input voltage produced by a voltage source; and

the second input voltage is a sum of a second dither signal produced by the programmable circuitry and the input voltage.

3 . The programmable circuitry of claim 1 , wherein:

the error value is a first error value; and

the programmable circuitry is further configured to:

determine a second output voltage from the second ADC responsive to the first ADC receiving the first input voltage and the second ADC receiving the second input voltage; and

determine a second error value of the second ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the second ADC.

4 . The programmable circuitry of claim 1 , wherein to estimate the error value, the programmable circuitry is configured to solve a system of equations based on: (a) the difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) the difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

5 . The programmable circuitry of claim 3 , further configured to:

determine multiple iterations of the first output voltage from the first ADC, the multiple iterations of the first output voltage within a range of voltages that is centered on a threshold voltage and has a width of one half of a step size of the first ADC; and

estimate an instance of the error value for each iteration of the first output voltage of the first ADC, wherein the error value is estimated at a frequency that enables detection of flicker noise.

6 . The programmable circuitry of claim 1 , wherein the first input voltage and the second input voltage are offset by half of a step size of the first ADC.

7 . The programmable circuitry of claim 1 , wherein the programmable circuitry is further configured to:

determine a third output voltage from the first ADC responsive to the first ADC receiving a third input voltage and the second ADC receiving the first input voltage; and

estimate a gain error of the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC, and (c) a difference between the third output voltage from the first ADC and the first output voltage from the first ADC.

8 . The programmable circuitry of claim 7 , wherein the first input voltage and the second input voltage are offset by one quarter of a step size of the first ADC.

9 . An apparatus comprising:

programmable circuitry;

a first analog to digital converter (ADC) having a first input terminal connected to the programmable circuitry and a second input connected to a voltage source; and

a second ADC having a first terminal connected to the programmable circuitry and a second input connected to the voltage source;

wherein the programmable circuitry is configured to:

determine a first output voltage from the first ADC responsive to the first ADC and a second ADC both receiving a first input voltage;

determine a first output voltage from the second ADC responsive to the first ADC and a second ADC both receiving the first input voltage;

determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and

determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

10 . The apparatus of claim 9 , wherein:

the first input voltage is a sum of a first dither signal produced by the programmable circuitry and an input voltage produced by the voltage source; and

the second input voltage is a sum of a second dither signal produced by the programmable circuitry and the input voltage.

11 . The apparatus of claim 9 , wherein:

the error value is a first error value; and

the programmable circuitry is further configured to:

determine a second output voltage from the second ADC responsive to the first ADC receiving the first input voltage and the second ADC receiving the second input voltage; and

determine a second error value for the second ADC based on: (a) a difference between the first output voltage from of the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the second ADC.

12 . The apparatus of claim 9 , wherein to estimate the error value, the programmable circuitry is configured to solve a system of equations based on: (a) the difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) the difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

13 . The apparatus of claim 9 , wherein the programmable circuitry is further configured to:

determine multiple iterations of the first output voltage from the first ADC, the multiple iterations of the first output voltage within a range of voltages that is centered on a threshold voltage and has a width of one half of a step size of the first ADC; and

estimate an instance of the error value for each iteration of the first output voltage from the first ADC, wherein the error value is estimated at a frequency that enables detection of flicker noise.

14 . The apparatus of claim 9 , wherein the first input voltage and the second input voltage are offset by half of a step size of the first ADC.

15 . The apparatus of claim 9 , wherein the programmable circuitry is further configured to:

determine a third output voltage from the first ADC responsive to the first ADC receiving a third input voltage and the second ADC receiving the first input voltage; and

estimate a gain error of the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC, and (c) a difference between the third output voltage from the first ADC and the first output voltage from the first ADC.

16 . The apparatus of claim 15 , wherein the first input voltage and the second input voltage are offset by one quarter of a step size of the first ADC.

17 . A method comprising:

determining, with programmable circuitry, a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage;

determining, with the programmable circuitry, a first output voltage from a second ADC responsive to the first ADC and a second ADC both receiving the first input voltage;

determining, with the programmable circuitry, a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and

determining, with the programmable circuitry, an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

18 . The method of claim 17 , wherein:

the first input voltage is a sum of a first dither signal produced by the programmable circuitry and an input voltage produced by a voltage source; and

the second input voltage is a sum of a second dither signal produced by the programmable circuitry and the input voltage.

19 . The method of claim 17 , wherein estimating the error value further includes: solving a system of equations based on: (a) the difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) the difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

20 . The method of claim 17 , wherein the first input voltage and the second input voltage are offset by half of a step size of the first ADC.

Assignments (1)

Continuity (1)

References Cited (9)