Semiconductor device
A semiconductor device includes: a substrate including an upper surface and a lower surface opposite to the upper surface; an active pattern disposed on the upper surface of the substrate and extending in a first direction; a field insulating film disposed on the upper surface of the substrate and covering a sidewall of the active pattern; a power rail disposed on the lower surface of the substrate and extending in the first direction; a trench formed in the substrate and exposing a portion of the power rail; and a metal pattern filling at least a portion of the trench and connected to the power rail, wherein a bottom surface of the trench is substantially coplanar with the lower surface of the substrate, wherein a sidewall of the trench has a convex shape, and wherein at least a portion of the field insulating film is disposed in the trench.
1 . A semiconductor device comprising:
a substrate including an upper surface and a lower surface opposite to the upper surface;
an active pattern disposed on the upper surface of the substrate and extending in a first direction;
a field insulating film disposed on the upper surface of the substrate and covering a sidewall of the active pattern;
a power rail disposed on the lower surface of the substrate and extending in the first direction;
a trench formed in the substrate and exposing a portion of the power rail; and
a metal pattern filling at least a portion of the trench and connected to the power rail,
wherein a bottom surface of the trench is substantially coplanar with the lower surface of the substrate,
wherein a sidewall of the trench has a convex shape, and
wherein at least a portion of the field insulating film is disposed in the trench.
2 . The semiconductor device of claim 1 , wherein a width, in a second direction, of the trench gradually increases and then decreases as the trench extends in a direction from the lower surface of the substrate toward the upper surface of the substrate, and
wherein the second direction intersects the first direction.
3 . The semiconductor device of claim 1 , wherein a width, in the first direction, of the trench gradually increases and then decreases as the trench extends in a direction from the lower surface of the substrate toward the upper surface of the substrate.
4 . The semiconductor device of claim 1 , wherein an interface between the field insulating film and the metal pattern is convex toward the power rail.
5 . The semiconductor device of claim 1 , further comprising:
a power rail via disposed on the metal pattern and connected to the power rail via the metal pattern.
6 . The semiconductor device of claim 5 , wherein at least a portion of the power rail via overlaps the substrate in a second direction intersecting the first direction.
7 . The semiconductor device of claim 5 , further comprising:
a source/drain pattern disposed on the active pattern; and
a source/drain contact disposed on the source/drain pattern,
wherein a bottom surface of the source/drain contact contacts an upper surface of the power rail via.
8 . The semiconductor device of claim 7 , wherein an upper surface of the source/drain pattern is substantially coplanar with the upper surface of the power rail via.
9 . The semiconductor device of claim 1 , wherein a slope of a sidewall of the trench gradually decreases and then increases as the sidewall of the trench extends in a direction from the lower surface of the substrate toward the upper surface of the substrate.
10 . The semiconductor device of claim 1 , wherein the active pattern includes a lower pattern and a plurality of sheet patterns spaced apart from the lower pattern.
11 . A semiconductor device comprising:
a substrate including an upper surface and a lower surface opposite to the upper surface;
an active pattern disposed on the upper surface of the substrate and extending in a first direction;
a gate electrode covering at least a portion of the active pattern and extending in a second direction interesting the first direction;
a power rail disposed on the lower surface of the substrate and extending in the first direction;
a metal pattern disposed in the substrate and connected to the power rail; and
a power rail via disposed on the metal pattern and disposed on one side of the gate electrode, wherein the power rail via is connected to the power rail via the metal pattern,
wherein a bottom surface of the metal pattern extends in a parallel to the lower surface of the substrate and is substantially coplanar with the lower surface of the substrate, and
wherein the metal pattern has a portion, wherein each of a width in the second direction of the portion of the metal pattern and a width in the first direction of the portion of the metal pattern gradually increases as the portion of the metal pattern extends in a direction from the lower surface of the substrate to the upper surface of the substrate.
12 . The semiconductor device of claim 11 , wherein a height from the lower surface of the substrate to a bottom surface of the power rail via is smaller than a thickness of the substrate.
13 . The semiconductor device of claim 11 , further comprising:
a source/drain pattern disposed on the active pattern and on one side of the gate electrode; and
a source/drain contact disposed on the source/drain pattern,
wherein the power rail via is connected to the source/drain contact.
14 . The semiconductor device of claim 13 , wherein an upper surface of the source/drain contact is substantially coplanar with an upper surface of the power rail via.
15 . The semiconductor device of claim 13 , wherein a bottom surface of the source/drain contact is in contact with an upper surface of the power rail via.
16 . The semiconductor device of claim 11 , wherein at least a portion of the power rail via is in direct contact with the power rail.
17 . The semiconductor device of claim 11 , wherein at least a portion of a sidewall of the power rail via directly contacts the substrate.
18 . The semiconductor device of claim 11 , wherein the active pattern includes a lower pattern and a plurality of sheet patterns spaced apart from the lower pattern.
19 . A semiconductor device comprising:
a substrate including an upper surface and a lower surface opposite to the upper surface;
an active pattern disposed on the upper surface of the substrate and extending in a first direction;
a gate electrode covering at least a portion of the active pattern and extending in a second direction intersecting the first direction;
a field insulating film disposed on the upper surface of the substrate and covering a sidewall of the active pattern;
a power rail disposed on the lower surface of the substrate and extending in the first direction;
a trench formed in the substrate and exposing a portion of the power rail, wherein the trench has a convexly shaped sidewall;
a metal pattern filling at least a portion of the trench and connected to the power rail;
a source/drain pattern disposed on the active pattern and on one side of the gate electrode;
a source/drain contact disposed on the source/drain pattern; and
a power rail via disposed on the metal pattern and disposed on one side of the gate electrode, wherein the power rail via is connected to the power rail via the metal pattern,
wherein a bottom surface of the trench is substantially coplanar with the lower surface of the substrate,
wherein at least a portion of the field insulating film is disposed in the trench, and
wherein each of a width in the first direction of the trench and a width in the second direction of the trench gradually increases and then decreases as the trench extends in a direction from the lower surface of the substrate to the upper surface of the substrate.
20 . The semiconductor device of claim 19 , wherein the active pattern includes a lower pattern and a plurality of sheet patterns spaced apart from the lower pattern.